fix(relinker): lower legacy packed reciprocal register instructions
This commit is contained in:
Scramblrrrr
parent
a11c8f7f70
commit
363d17985e
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@ -49,6 +49,8 @@ inline constexpr Entry kMovntss = {"MOVNTSS", nullptr, 0};
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inline constexpr Entry kMovntsd = {"MOVNTSD", nullptr, 0};
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inline constexpr Entry kVrcpps = {"VRCPPS", nullptr, 0};
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inline constexpr Entry kVrsqrtps = {"VRSQRTPS", nullptr, 0};
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inline constexpr Entry kRcpps = {"RCPPS", nullptr, 0};
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inline constexpr Entry kRsqrtps = {"RSQRTPS", nullptr, 0};
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inline constexpr Entry kSha256rnds2 = {"SHA256RNDS2", nullptr, 0};
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inline constexpr Entry kSha256msg1 = {"SHA256MSG1", nullptr, 0};
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inline constexpr Entry kSha256msg2 = {"SHA256MSG2", nullptr, 0};
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@ -16,9 +16,10 @@ struct ReciprocalOperands {
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ReciprocalOperation Operation;
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std::uint8_t Destination;
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std::uint8_t Source;
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bool Vex;
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};
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[[nodiscard]] std::optional<ReciprocalOperands> DecodeVexReciprocal(const std::uint8_t* data, std::size_t length);
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[[nodiscard]] std::optional<ReciprocalOperands> DecodeReciprocal(const std::uint8_t* data, std::size_t length);
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}
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@ -41,6 +41,8 @@ const Entry& _sse4aEntry(const Sse4aOperands& operands) {
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}
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const Entry& _reciprocalEntry(const ReciprocalOperands& operands) {
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if (!operands.Vex)
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return operands.Operation == ReciprocalOperation::ReciprocalSquareRoot ? kRsqrtps : kRcpps;
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return operands.Operation == ReciprocalOperation::ReciprocalSquareRoot ? kVrsqrtps : kVrcpps;
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}
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@ -239,7 +241,7 @@ std::optional<Amd64OnlyMatch> Amd64OnlyInstructionMatcher::MatchSequence(
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if (name == nullptr)
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name = kClzero.Name;
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_clzeroLowering.EmitOutOfLine(body, operands);
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} else if (const auto reciprocal = DecodeVexReciprocal(instr.Data, instr.Length)) {
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} else if (const auto reciprocal = DecodeReciprocal(instr.Data, instr.Length)) {
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if (name == nullptr)
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name = _reciprocalEntry(*reciprocal).Name;
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_reciprocalLowering.EmitOutOfLine(body, *reciprocal);
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@ -254,7 +256,7 @@ std::optional<Amd64OnlyMatch> Amd64OnlyInstructionMatcher::MatchSequence(
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}
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_moveTrailing(body, trailing);
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const DecodedInstruction first{instructions.front().data(), instructions.front().size()};
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const bool optional = DecodeVexReciprocal(first.Data, first.Length).has_value() || (_target == Amd64OnlyTarget::Rosetta && first.IsRdpid());
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const bool optional = DecodeReciprocal(first.Data, first.Length).has_value() || (_target == Amd64OnlyTarget::Rosetta && first.IsRdpid());
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return _trampoline(name, instructions.front().size(), body.Finish(), optional);
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}
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@ -289,7 +291,7 @@ std::optional<Amd64OnlyMatch> Amd64OnlyInstructionMatcher::Match(
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if (instr.IsMwaitx())
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return _validWait(instr) ? _inPlace(kMwaitx, length, std::vector<std::uint8_t>(kPause.Bytes, kPause.Bytes + kPause.Size)) : _unsupported(kMwaitx, length);
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if (const auto reciprocal = DecodeVexReciprocal(data, length)) {
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if (const auto reciprocal = DecodeReciprocal(data, length)) {
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return _trampoline(_reciprocalEntry(*reciprocal).Name, length, _outOfLine(length, trailing, [&](StubBodyBuilder& body) { _reciprocalLowering.EmitOutOfLine(body, *reciprocal); }), true);
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}
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@ -46,11 +46,15 @@ void ReciprocalLowering::EmitOutOfLine(StubBodyBuilder& body, const ReciprocalOp
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body.SsePlain({0x0F, kSqrtps}, scratch, operands.Source);
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body.RipOperand({0x0F, kMovaps}, dst, _ones());
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body.SsePlain({0x0F, kDivps}, dst, scratch);
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_vexMovaps(body, dst, dst);
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if (operands.Vex)
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_vexMovaps(body, dst, dst);
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} else {
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body.RipOperand({0x0F, kMovaps}, scratch, _ones());
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body.SsePlain({0x0F, kDivps}, scratch, operands.Source);
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_vexMovaps(body, dst, scratch);
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if (operands.Vex)
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_vexMovaps(body, dst, scratch);
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else
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body.SsePlain({0x0F, kMovaps}, dst, scratch);
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}
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body.Restore(scratch);
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}
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@ -12,14 +12,15 @@ constexpr std::uint8_t kOpcodeRcpps = 0x53;
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}
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std::optional<ReciprocalOperands> DecodeVexReciprocal(const std::uint8_t* data, const std::size_t length) {
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std::optional<ReciprocalOperands> DecodeReciprocal(const std::uint8_t* data, const std::size_t length) {
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using namespace X64OpcodeConstants;
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if (length < 4)
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if (length < 3)
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return std::nullopt;
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bool registerExtension = false;
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bool rmExtension = false;
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std::uint8_t payload = 0;
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std::size_t opcodeOffset = 0;
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bool vex = true;
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if (data[0] == OneByteVex2 && length == 4) {
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registerExtension = (data[1] & 0x80) == 0;
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payload = data[1];
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@ -31,13 +32,21 @@ std::optional<ReciprocalOperands> DecodeVexReciprocal(const std::uint8_t* data,
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rmExtension = (data[1] & 0x20) == 0;
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payload = data[2];
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opcodeOffset = 3;
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} else if (data[0] == TwoByteOpcodeEscape && length == 3) {
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opcodeOffset = 1;
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vex = false;
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} else if (data[0] >= RexMin && data[0] <= RexMax && length == 4 && data[1] == TwoByteOpcodeEscape) {
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registerExtension = (data[0] & 0x04) != 0;
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rmExtension = (data[0] & 0x01) != 0;
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opcodeOffset = 2;
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vex = false;
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} else {
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return std::nullopt;
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}
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const auto vvvv = static_cast<std::uint8_t>((payload >> 3) & 0x0F);
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const bool wide = (payload & 0x04) != 0;
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const auto pp = static_cast<std::uint8_t>(payload & 0x03);
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if (vvvv != kVexUnusedRegister || wide || pp != 0)
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if (vex && (vvvv != kVexUnusedRegister || wide || pp != 0))
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return std::nullopt;
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const auto opcode = data[opcodeOffset];
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if (opcode != kOpcodeRsqrtps && opcode != kOpcodeRcpps)
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@ -49,6 +58,7 @@ std::optional<ReciprocalOperands> DecodeVexReciprocal(const std::uint8_t* data,
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operands.Operation = opcode == kOpcodeRsqrtps ? ReciprocalOperation::ReciprocalSquareRoot : ReciprocalOperation::Reciprocal;
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operands.Destination = static_cast<std::uint8_t>(((modrm >> ModRmRegShift) & ModRmRegMask) | (registerExtension ? 8 : 0));
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operands.Source = static_cast<std::uint8_t>((modrm & ModRmRmMask) | (rmExtension ? 8 : 0));
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operands.Vex = vex;
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return operands;
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}
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@ -700,17 +700,23 @@ void converterRosetta() {
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}
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void reciprocalOperands() {
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const auto vex2 = Codegen::DecodeVexReciprocal(Bytes{0xC5, 0xF8, 0x52, 0xD5}.data(), 4);
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const auto vex2 = Codegen::DecodeReciprocal(Bytes{0xC5, 0xF8, 0x52, 0xD5}.data(), 4);
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require(vex2 && vex2->Operation == Codegen::ReciprocalOperation::ReciprocalSquareRoot && vex2->Destination == 2 && vex2->Source == 5, "VEX2 VRSQRTPS was not decoded");
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const auto vex2High = Codegen::DecodeVexReciprocal(Bytes{0xC5, 0x78, 0x53, 0xC1}.data(), 4);
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const auto vex2High = Codegen::DecodeReciprocal(Bytes{0xC5, 0x78, 0x53, 0xC1}.data(), 4);
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require(vex2High && vex2High->Operation == Codegen::ReciprocalOperation::Reciprocal && vex2High->Destination == 8 && vex2High->Source == 1, "VEX2 VRCPPS with a high destination was not decoded");
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const auto vex3 = Codegen::DecodeVexReciprocal(Bytes{0xC4, 0x41, 0x78, 0x52, 0xC9}.data(), 5);
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const auto vex3 = Codegen::DecodeReciprocal(Bytes{0xC4, 0x41, 0x78, 0x52, 0xC9}.data(), 5);
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require(vex3 && vex3->Destination == 9 && vex3->Source == 9, "VEX3 VRSQRTPS with high registers was not decoded");
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require(!Codegen::DecodeVexReciprocal(Bytes{0xC5, 0xFC, 0x52, 0xD5}.data(), 4), "256-bit VRSQRTPS must stay native");
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require(!Codegen::DecodeVexReciprocal(Bytes{0xC5, 0xFA, 0x52, 0xD5}.data(), 4), "VRSQRTSS must stay native");
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require(!Codegen::DecodeVexReciprocal(Bytes{0xC5, 0xF8, 0x52, 0x10}.data(), 4), "Memory form must stay native");
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require(!Codegen::DecodeVexReciprocal(Bytes{0xC5, 0xF8, 0x51, 0xD5}.data(), 4), "VSQRTPS is not a reciprocal");
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require(!Codegen::DecodeVexReciprocal(Bytes{0x0F, 0x52, 0xD5}.data(), 3), "Legacy RSQRTPS must stay native");
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require(!Codegen::DecodeReciprocal(Bytes{0xC5, 0xFC, 0x52, 0xD5}.data(), 4), "256-bit VRSQRTPS must stay native");
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require(!Codegen::DecodeReciprocal(Bytes{0xC5, 0xFA, 0x52, 0xD5}.data(), 4), "VRSQRTSS must stay native");
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require(!Codegen::DecodeReciprocal(Bytes{0xC5, 0xF8, 0x52, 0x10}.data(), 4), "Memory form must stay native");
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require(!Codegen::DecodeReciprocal(Bytes{0xC5, 0xF8, 0x51, 0xD5}.data(), 4), "VSQRTPS is not a reciprocal");
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require(vex2->Vex && vex2High->Vex && vex3->Vex, "VEX reciprocals must clear the upper vector bits");
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const auto legacy = Codegen::DecodeReciprocal(Bytes{0x0F, 0x52, 0xD5}.data(), 3);
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require(legacy && !legacy->Vex && legacy->Operation == Codegen::ReciprocalOperation::ReciprocalSquareRoot && legacy->Destination == 2 && legacy->Source == 5, "Legacy RSQRTPS was not decoded");
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const auto legacyHigh = Codegen::DecodeReciprocal(Bytes{0x45, 0x0F, 0x53, 0xC9}.data(), 4);
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require(legacyHigh && !legacyHigh->Vex && legacyHigh->Operation == Codegen::ReciprocalOperation::Reciprocal && legacyHigh->Destination == 9 && legacyHigh->Source == 9, "Legacy RCPPS with high registers was not decoded");
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for (const Bytes& unsupported : {Bytes{0xF3, 0x0F, 0x52, 0xD5}, Bytes{0xF3, 0x0F, 0x53, 0xD5}, Bytes{0x0F, 0x52, 0x10}, Bytes{0x0F, 0x53, 0x10}, Bytes{0x0F, 0x51, 0xD5}, Bytes{0x0F, 0x52}, Bytes{0x45, 0x0F, 0x53}})
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require(!Codegen::DecodeReciprocal(unsupported.data(), unsupported.size()), "An unsupported legacy reciprocal encoding was accepted");
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}
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void converterReciprocal() {
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@ -744,6 +750,27 @@ void converterReciprocal() {
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require(moved.Trampolines.size() == 1 && moved.KeptCount == 0 && moved.Bytes == ripRelative && moved.Trampolines[0].Length == 10, "VRSQRTPS did not absorb the following RIP-relative load");
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const auto& movedSite = moved.Trampolines[0];
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require(movedSite.Relocations.size() == 1 && movedSite.Relocations[0].DisplacementOffset == movedSite.ReturnBranchOffset - 4 && movedSite.Relocations[0].InstructionEnd == movedSite.ReturnBranchOffset && movedSite.Relocations[0].SiteTarget == 10 + 0x10, "Absorbed RIP-relative load has the wrong relocation");
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for (const std::uint8_t opcode : {std::uint8_t{0x52}, std::uint8_t{0x53}}) {
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const std::string name = opcode == 0x52 ? "RSQRTPS" : "RCPPS";
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for (const Bytes& instruction : {Bytes{0x0F, opcode, 0xD5}, Bytes{0x45, 0x0F, opcode, 0xC9}}) {
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auto legacyFile = file;
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Bytes legacyText = instruction;
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legacyText.insert(legacyText.end(), {0x90, 0x90, 0xC3});
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std::copy(legacyText.begin(), legacyText.end(), legacyFile.begin() + 0x200);
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const auto legacy = converter->Convert(legacyFile, {segmentHeader(legacyText.size())});
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require(legacy.Trampolines.size() == 1 && legacy.KeptCount == 0 && legacy.Reports[0].InstructionName == name && legacy.Trampolines[0].Length == 5, "Legacy reciprocal did not absorb enough instructions for a jump");
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legacyText = instruction;
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legacyText.push_back(0xC3);
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std::copy(legacyText.begin(), legacyText.end(), legacyFile.begin() + 0x200);
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const auto kept = converter->Convert(legacyFile, {segmentHeader(legacyText.size())});
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require(kept.Trampolines.empty() && kept.KeptCount == 1 && kept.Bytes == legacyFile && kept.Reports[0].InstructionName == name, "Legacy reciprocal before a return must stay native");
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}
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}
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auto sequenceFile = file;
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const Bytes sequenceText = {0x0F, 0x52, 0xD5, 0xC5, 0xF8, 0x53, 0xC1, 0xC3};
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std::copy(sequenceText.begin(), sequenceText.end(), sequenceFile.begin() + 0x200);
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const auto sequence = converter->Convert(sequenceFile, {segmentHeader(sequenceText.size())});
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require(sequence.Trampolines.size() == 1 && sequence.KeptCount == 0 && sequence.Trampolines[0].Length == 7 && sequence.Reports[0].InstructionName == "RSQRTPS", "Mixed legacy and VEX reciprocals were not lowered together");
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}
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void converterStrayRex() {
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@ -1037,10 +1064,10 @@ void reciprocalExecution() {
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for (const auto& lanes : inputs) {
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const std::uint64_t source[2] = {packLanes(lanes, 0), packLanes(lanes, 2)};
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const std::uint64_t destination[2] = {0x1111111111111111ull, 0x2222222222222222ull};
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for (const bool squareRoot : {true, false}) {
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for (const bool squareRoot : {true, false}) for (const bool vex : {false, true}) {
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const std::uint8_t opcode = squareRoot ? 0x52 : 0x53;
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const Bytes distinct = {0xC5, 0xF8, opcode, 0xD5};
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const Bytes same = {0xC5, 0xF8, opcode, 0xD2};
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const Bytes distinct = vex ? Bytes{0xC5, 0xF8, opcode, 0xD5} : Bytes{0x0F, opcode, 0xD5};
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const Bytes same = vex ? Bytes{0xC5, 0xF8, opcode, 0xD2} : Bytes{0x0F, opcode, 0xD2};
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const auto distinctOut = runRegisterFormStub(distinct, destination, source);
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const auto sameOut = runRegisterFormStub(same, source, source);
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float distinctLanes[4];
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@ -1049,8 +1076,8 @@ void reciprocalExecution() {
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std::memcpy(sameLanes, sameOut.data(), sizeof(sameLanes));
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for (std::size_t lane = 0; lane < 4; ++lane) {
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const float expected = squareRoot ? 1.0f / std::sqrt(lanes[lane]) : 1.0f / lanes[lane];
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require(sameLane(expected, distinctLanes[lane]), "VRSQRTPS/VRCPPS stub is not correctly rounded");
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require(sameLane(expected, sameLanes[lane]), "VRSQRTPS/VRCPPS stub with equal operands is not correctly rounded");
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require(sameLane(expected, distinctLanes[lane]), "Packed reciprocal stub is not correctly rounded");
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require(sameLane(expected, sameLanes[lane]), "Packed reciprocal stub with equal operands is not correctly rounded");
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}
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}
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}
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@ -10,6 +10,7 @@
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#include <elfpatcher/windows/WindowsTrampolineBuilder.hpp>
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#include <io/BufferUtils.hpp>
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#include <array>
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#include <cmath>
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#include <cstring>
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#include <functional>
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#include <iostream>
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@ -59,6 +60,7 @@ struct alignas(16) State {
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std::uint64_t RspBefore;
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std::uint64_t RspAfter;
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std::uint8_t RedZone[128];
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std::uint8_t Ymm[16][32];
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};
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constexpr std::uint64_t kCanary = 0xA5C3E17B9D24F608ull;
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@ -94,6 +96,11 @@ void movdquXmmRsp(Bytes& code, const std::uint8_t reg, const bool store, const s
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emitU32(code, offset);
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}
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void vmovdquYmmRbx(Bytes& code, const std::uint8_t reg, const bool store) {
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emit(code, {0xC4, static_cast<std::uint8_t>(reg >= 8 ? 0x61 : 0xE1), 0x7E, static_cast<std::uint8_t>(store ? 0x7F : 0x6F), static_cast<std::uint8_t>(0x83 | ((reg & 7) << 3))});
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emitU32(code, static_cast<std::uint32_t>(offsetof(State, Ymm)) + reg * 32);
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}
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class Harness {
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public:
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Harness() : _memory(VirtualAlloc(nullptr, kSize, MEM_COMMIT | MEM_RESERVE, PAGE_EXECUTE_READWRITE)) {
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@ -104,7 +111,7 @@ public:
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VirtualFree(_memory, 0, MEM_RELEASE);
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}
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void Run(const Bytes& body, const std::size_t returnBranchOffset, State& state) const {
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void Run(const Bytes& body, const std::size_t returnBranchOffset, State& state, const bool wide = false) const {
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Bytes code;
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emit(code, {0x53, 0x55, 0x56, 0x57, 0x41, 0x54, 0x41, 0x55, 0x41, 0x56, 0x41, 0x57, 0x48, 0x81, 0xEC, 0xA8, 0x00, 0x00, 0x00});
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for (std::uint8_t reg = 6; reg < 16; ++reg) movdquXmmRsp(code, reg, true, (reg - 6) * 16);
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@ -115,7 +122,12 @@ public:
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for (int slot = 0; slot < 16; ++slot) emit(code, {0x48, 0x89, 0x44, 0x24, static_cast<std::uint8_t>(-128 + slot * 8)});
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emit(code, {0x48, 0x89, 0xA3});
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emitU32(code, kRspBeforeOffset);
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for (std::uint8_t reg = 0; reg < 16; ++reg) movdquXmmRbx(code, reg, false);
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for (std::uint8_t reg = 0; reg < 16; ++reg) {
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if (wide)
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vmovdquYmmRbx(code, reg, false);
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else
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movdquXmmRbx(code, reg, false);
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}
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code.push_back(0xE9);
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const auto jumpOffset = code.size();
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emitU32(code, 0);
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@ -129,6 +141,8 @@ public:
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emit(code, {0x9C, 0x8F, 0x83});
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emitU32(code, kFlagsOutOffset);
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for (std::uint8_t reg = 0; reg < 16; ++reg) movdquXmmRbx(code, reg, true);
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if (wide)
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for (std::uint8_t reg = 0; reg < 16; ++reg) vmovdquYmmRbx(code, reg, true);
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for (std::uint8_t reg = 6; reg < 16; ++reg) movdquXmmRsp(code, reg, false, (reg - 6) * 16);
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emit(code, {0x48, 0x81, 0xC4, 0xA8, 0x00, 0x00, 0x00, 0x41, 0x5F, 0x41, 0x5E, 0x41, 0x5D, 0x41, 0x5C, 0x5F, 0x5E, 0x5D, 0x5B, 0xC3});
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code.resize(Io::AlignUp(code.size(), std::size_t{16}), 0xCC);
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@ -219,6 +233,69 @@ void requireEnvironment(const State& input, const State& state, const std::uint1
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}
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}
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void reciprocalExecution() {
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const Harness harness;
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const auto matcher = Codegen::MakeAmd64OnlyInstructionMatcher();
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const bool wide = __builtin_cpu_supports("avx");
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const float inputs[][4] = {
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{1.0f, 4.0f, 0.25f, 2.0f},
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{0.0f, -0.0f, INFINITY, -1.0f},
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{1.00000012f, 0.99999994f, 3.0e-38f, 1.0e30f},
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{NAN, -INFINITY, -4.0f, 16.0f}};
|
||||
for (const bool vex : {false, true}) {
|
||||
if (vex && !wide)
|
||||
continue;
|
||||
for (const std::uint8_t opcode : {std::uint8_t{0x52}, std::uint8_t{0x53}}) {
|
||||
for (const std::uint8_t destination : {std::uint8_t{0}, std::uint8_t{2}, std::uint8_t{9}, std::uint8_t{15}}) {
|
||||
for (const std::uint8_t source : {destination, std::uint8_t{0}, std::uint8_t{5}, std::uint8_t{14}}) {
|
||||
Bytes site;
|
||||
if (vex) {
|
||||
emit(site, {0xC4, static_cast<std::uint8_t>((destination >= 8 ? 0 : 0x80) | 0x40 | (source >= 8 ? 0 : 0x20) | 1), 0x78});
|
||||
} else {
|
||||
const auto rex = static_cast<std::uint8_t>(0x40 | (destination >= 8 ? 4 : 0) | (source >= 8 ? 1 : 0));
|
||||
if (rex != 0x40)
|
||||
site.push_back(rex);
|
||||
site.push_back(0x0F);
|
||||
}
|
||||
emit(site, {opcode, static_cast<std::uint8_t>(0xC0 | ((destination & 7) << 3) | (source & 7))});
|
||||
const auto match = matcher->Match(site.data(), site.size());
|
||||
require(match && match->Lowering == Codegen::Amd64OnlyLowering::Trampoline, "Packed reciprocal was not lowered");
|
||||
for (const auto& lanes : inputs) {
|
||||
State input{};
|
||||
for (std::size_t reg = 0; reg < 16; ++reg) {
|
||||
for (std::size_t byte = 0; byte < 16; ++byte) {
|
||||
input.Xmm[reg][byte] = static_cast<std::uint8_t>(reg * 16 + byte);
|
||||
input.Ymm[reg][byte + 16] = static_cast<std::uint8_t>(reg * 16 + byte + 1);
|
||||
}
|
||||
}
|
||||
std::memcpy(input.Xmm[source], lanes, sizeof(lanes));
|
||||
for (std::size_t reg = 0; reg < 16; ++reg)
|
||||
std::memcpy(input.Ymm[reg], input.Xmm[reg], 16);
|
||||
input.FlagsIn = 0xAC7;
|
||||
State state = input;
|
||||
harness.Run(match->StubBody, match->ReturnBranchOffset, state, wide);
|
||||
++g_executions;
|
||||
float actual[4];
|
||||
std::memcpy(actual, state.Xmm[destination], sizeof(actual));
|
||||
for (std::size_t lane = 0; lane < 4; ++lane) {
|
||||
const float expected = opcode == 0x52 ? 1.0f / std::sqrt(lanes[lane]) : 1.0f / lanes[lane];
|
||||
require(std::isnan(expected) ? std::isnan(actual[lane]) : std::memcmp(&expected, &actual[lane], sizeof(float)) == 0, "Packed reciprocal result differs from division and square root");
|
||||
}
|
||||
requireEnvironment(input, state, static_cast<std::uint16_t>(1u << destination), "packed reciprocal");
|
||||
if (wide) {
|
||||
const std::uint8_t zero[16] = {};
|
||||
for (std::size_t reg = 0; reg < 16; ++reg) {
|
||||
const auto* expected = vex && reg == destination ? zero : input.Ymm[reg] + 16;
|
||||
require(std::memcmp(state.Ymm[reg] + 16, expected, 16) == 0, "Packed reciprocal changed the wrong upper YMM bits");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void executeCase(const Harness& harness, const Codegen::IAmd64OnlyInstructionMatcher& matcher, const Case& item, std::mt19937_64& random, const int images) {
|
||||
const auto site = encode(item);
|
||||
const auto match = matcher.Match(site.data(), site.size());
|
||||
|
|
@ -643,6 +720,7 @@ void peBuilder() {
|
|||
int main() {
|
||||
try {
|
||||
cpuExecution();
|
||||
reciprocalExecution();
|
||||
peBuilder();
|
||||
std::cout << "AMD64-only Windows tests passed (" << g_executions << " lowered sequences executed)\n";
|
||||
} catch (const std::exception& error) {
|
||||
|
|
|
|||
|
|
@ -513,7 +513,7 @@ Throughout the project, every function at every stage either **does exactly what
|
|||
- [UINT16_ABGR color exports](../../core/libs/prx/libSceAgcDriver/Graphics/src/State.cpp) (libSceAgcDriver) - export format 7 is accepted only into an unsigned integer target, and each 16-bit value reaches the target unchanged; a value beyond a narrower target's range (`R8_UINT`) is undefined in Vulkan, and whether the console clamps or truncates it is not confirmed. SINT16_ABGR (8) throws
|
||||
- `--to-intel` guest module trampolines are covered only by a synthetic relinker test; no game title has been verified with them on Linux or Windows.
|
||||
- `--to-rosetta` lowers what Rosetta lacks on top of `--to-intel` ([matcher](../../core/relinker/codegen/src/x86/Amd64OnlyInstructionMatcher.cpp)). Rosetta runs AVX2, FMA, BMI1/2, F16C and MOVBE but reports none of them through CPUID, so code that checks CPUID takes its baseline path. RDSEED becomes RDRAND and CLWB a NOP. RDPID returns processor 0, because Rosetta's TSC_AUX is the constant 0xAAAAAAAB; the same value reaches RDTSCP's ECX, which is not converted. ADCX/ADOX fault under Rosetta and are not converted: compilers do not emit them, and code that checks CPUID sees no ADX. The conversions are covered by the converter tests; that the converted code runs under Rosetta was checked on an M5 Max only, outside this repository's CI.
|
||||
- `--to-intel` replaces the approximate VEX.128 register forms of VRSQRTPS and VRCPPS with [correctly rounded](../../core/relinker/codegen/src/x86/ReciprocalLowering.cpp) 1/sqrt(x) and 1/x, not with the AMD approximation: its tables are not public. Intel's approximation of 1/sqrt(1.0) is 0x3F7FF000, and two Newton-Raphson steps on it settle on 0.99999994 instead of 1.0; a renormalised identity quaternion then turns into a NaN axis in PPSA21564, which the console does not show. Refined results now reach the exact value; unrefined ones can still differ from the console in the low bits. Each site costs an out-of-line stub (two jumps, a spill below the red zone, SQRTPS/DIVPS). The 256-bit, scalar, legacy and memory forms keep the native instruction, as does a 4-byte site with no movable instruction after it for the jump (5 sites in PPSA21564, counted before a following RIP-relative instruction could move into the stub; not recounted).
|
||||
- `--to-intel` replaces the approximate legacy SSE and VEX.128 register forms of RSQRTPS/RCPPS and VRSQRTPS/VRCPPS with [correctly rounded](../../core/relinker/codegen/src/x86/ReciprocalLowering.cpp) 1/sqrt(x) and 1/x, not with the AMD approximation: its tables are not public. Intel's approximation of 1/sqrt(1.0) is 0x3F7FF000, and two Newton-Raphson steps on it settle on 0.99999994 instead of 1.0; a renormalised identity quaternion then turns into a NaN axis in PPSA21564, which the console does not show. Refined results now reach the exact value; unrefined ones can still differ from the console in the low bits. Each site costs an out-of-line stub (two jumps, a spill below the red zone, SQRTPS/DIVPS). Legacy SSE forms preserve the destination's upper YMM bits; VEX forms clear them. The 256-bit, scalar and memory forms keep the native instruction, as does a site shorter than 5 bytes with no movable instruction after it for the jump (5 sites in PPSA21564, counted before a following RIP-relative instruction could move into the stub; not recounted).
|
||||
- [sceKeyboardGetKey2Char](../../core/libs/prx/libSceKeyboard/src/keyboard_impl.cpp) (libSceKeyboard) translates the 101-key (US) arrangement and the alphanumeric layer of the 106-key (Japanese) one, which follows the JIS layout of the HID usages: the Yen (0x89) and Ro (0x87) keys return `\` (0x5C) unshifted, as JIS X 0201 places the yen sign there; whether the console returns U+00A5 instead is unverified. With the Kana LED (bit 4, the HID position) set the 106-key arrangement throws, as the kana the console returns are unknown. Ctrl and Alt do not change the character.
|
||||
- [sceAudioOut2Set3DLatency](../../core/libs/prx/libSceAudioOut/src/AudioOut2System.cpp) and [sceAudioOut2MasteringInit, sceAudioOut2MasteringTerm and sceAudioOut2MasteringSetParam](../../core/libs/prx/libSceAudioOut/src/AudioOut2Mastering.cpp) (libSceAudioOut) have no effect: there is no 3D rendering or mastering stage.
|
||||
- [sceImeKeyboardGetInfo](../../core/libs/prx/libSceIme/Export.cpp) (libSceIme) returns `0x80bc0023` (no resource id) for every id while a keyboard is open, since the IME keyboard never reports a connected device. [sceImeKeyboardSetMode](../../core/libs/prx/libSceIme/Export.cpp) validates the mode bits but the mode has no effect, as no IME keyboard events are delivered.
|
||||
|
|
|
|||
Loading…
Reference in New Issue