From 3c6b0af6f7641793c4aec671102857851520d927 Mon Sep 17 00:00:00 2001 From: adriadam10 Date: Sun, 27 Sep 2026 18:21:34 +0200 Subject: [PATCH] feat(tools): add progress map for system libraries and shader instructions tools/progress.py counts implemented prx functions and RDNA instructions recognized by the shader recompiler, and renders treemaps, badges and an index page. The Progress workflow deploys them to GitHub Pages on every push to main, so nothing generated is committed to the repository. Co-Authored-By: Claude Opus 5.5 (1M context) --- .github/workflows/progress.yml | 30 + README.md | 10 + tools/README.md | 27 + tools/progress.py | 241 +++++++ tools/rdna_isa.txt | 1169 ++++++++++++++++++++++++++++++++ 5 files changed, 1477 insertions(+) create mode 100644 .github/workflows/progress.yml create mode 100644 tools/README.md create mode 100644 tools/progress.py create mode 100644 tools/rdna_isa.txt diff --git a/.github/workflows/progress.yml b/.github/workflows/progress.yml new file mode 100644 index 000000000..93e9f0600 --- /dev/null +++ b/.github/workflows/progress.yml @@ -0,0 +1,30 @@ +name: Progress + +on: + push: + branches: [main] + workflow_dispatch: + +permissions: + contents: read + pages: write + id-token: write + +concurrency: + group: pages + cancel-in-progress: false + +jobs: + progress: + runs-on: ubuntu-latest + environment: + name: github-pages + url: ${{ steps.deployment.outputs.page_url }} + steps: + - uses: actions/checkout@v7 + - run: python3 tools/progress.py out + - uses: actions/upload-pages-artifact@v5 + with: + path: out + - id: deployment + uses: actions/deploy-pages@v5 diff --git a/README.md b/README.md index 2f746fbfd..7f6c47a63 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,11 @@ # About +[![libraries](https://boykopovar.github.io/AnyPS5/badge-libraries.svg)](https://boykopovar.github.io/AnyPS5/) [![shaders](https://boykopovar.github.io/AnyPS5/badge-shaders.svg)](https://boykopovar.github.io/AnyPS5/) + +[![progress map](https://boykopovar.github.io/AnyPS5/progress.svg)](https://boykopovar.github.io/AnyPS5/) + +* System libraries: percentage of the functions known to the project so far (declared in [core/libs/prx](core/libs/prx)), not of every PS5 system function. The total grows as more functions are declared. + Tool for automatic executables porting to Linux and Windows. Includes a [relinker](core/relinker) that converts executable to the target system's native format and implementations of [system prx libraries](core/libs/prx) suitable for dynamic linking. No emulation or separate runtime process. @@ -14,6 +20,10 @@ The [shader recompiler](core/shader/recompiler/Recompiler.cpp) successfully prod The real game reaches the logo, main menu, and [gameplay](https://gist.github.com/user-attachments/assets/81d28e9b-c237-4545-b2ca-720071129816) with audio. +[Progress](https://boykopovar.github.io/AnyPS5/), generated by [tools/progress.py](tools/progress.py) on every push to `main`: +- **System libraries\***: each block is a [prx library](core/libs/prx) sized by its functions; green is implemented, blue still calls `NotImplemented`. The total only includes functions already declared in the project, not every function of the PS5 firmware. +- **GPU shader instructions**: each block is an instruction encoding of the AMD RDNA 1 + RDNA 2 [instruction list](tools/rdna_isa.txt); green is recognized by the [shader recompiler](core/shader/recompiler). + [Technical debt of the project](docs/TechnicalDebt.md), [code style conventions](docs/CONVENTIONS.md) ## Build diff --git a/tools/README.md b/tools/README.md new file mode 100644 index 000000000..5a1481df6 --- /dev/null +++ b/tools/README.md @@ -0,0 +1,27 @@ +# Tools + +## progress.py + +Generates the progress map shown in the main [README](../README.md). + +```sh +python3 tools/progress.py +``` + +Requires only Python 3.9+ with the standard library. It writes: + +- `progress.svg`: treemaps for system libraries and GPU shader instructions +- `badge-libraries.svg`, `badge-shaders.svg`: percentage badges +- `index.html`: the map with per-library and per-encoding tables +- `progress.json`: raw numbers + +The [Progress workflow](../.github/workflows/progress.yml) runs it on every push to `main` and deploys the output to GitHub Pages, so nothing generated is committed to the repository. + +### What is measured + +- **System libraries**: functions defined in [core/libs/prx](../core/libs/prx). A function is implemented when it no longer calls `NotImplemented_nid_no_patch`. The total only includes functions already declared in the project, not every function of the PS5 firmware. +- **GPU shader instructions**: instructions from [rdna_isa.txt](rdna_isa.txt) that appear in `RdnaOpcode` of the [shader recompiler](../core/shader/recompiler/RdnaDecoder). FLAT opcodes also count for their GLOBAL and SCRATCH forms, since the decoder accepts all three segments. Decoded opcodes missing from AMD's public list are not counted. + +## rdna_isa.txt + +The AMD RDNA 1 + RDNA 2 instruction list (name and primary encoding), extracted from the [AMD Machine-Readable GPU ISA Specification](https://gpuopen.com/machine-readable-isa/) (MIT License). diff --git a/tools/progress.py b/tools/progress.py new file mode 100644 index 000000000..d90d7b6af --- /dev/null +++ b/tools/progress.py @@ -0,0 +1,241 @@ +import argparse +import json +import os +import re +from html import escape +from pathlib import Path + +ROOT = Path(__file__).resolve().parent.parent +PRX = ROOT / "core" / "libs" / "prx" +OPCODES = ROOT / "core" / "shader" / "recompiler" / "RdnaDecoder" / "include" / "RdnaDecoder" / "RdnaOpcode.hpp" +ISA = Path(__file__).resolve().parent / "rdna_isa.txt" +SOURCE = f'https://github.com/{os.environ.get("GITHUB_REPOSITORY", "boykopovar/AnyPS5")}/blob/main' +DEFINITION = re.compile(r"\bAPS5_VABI\s+(\w+)\s*\([^;{]*\)\s*(?:noexcept\s*)?\{") +STUB = "NotImplemented_nid_no_patch" +FLAT_SEGMENTS = ("GLOBAL_", "SCRATCH_") +OPCODE_SENTINELS = {"Invalid", "Count", "Unknown", "Unsupported"} +OPCODE_ALIASES = { + "TBufferLoadFormatX": "TBUFFER_LOAD_FORMAT_X", + "TBufferLoadFormatXyzw": "TBUFFER_LOAD_FORMAT_XYZW", + "ExpMrt": "EXP", + "ExpPos": "EXP", + "ExpParam": "EXP", + "VAddcU32": "V_ADD_CO_CI_U32", + "VMadMixloF16": "V_FMA_MIXLO_F16", + "VMadMixhiF16": "V_FMA_MIXHI_F16", +} +PANEL_WIDTH, GAP, MAP_HEIGHT, HEADER = 495, 10, 280, 30 +DONE_COLOR, TODO_COLOR, BORDER, TEXT = "#2ea043", "#1f6feb", "#0d1117", "#ffffff" + + +def body_end(text, start): + depth = 0 + for i in range(start, len(text)): + if text[i] == "{": + depth += 1 + elif text[i] == "}": + depth -= 1 + if depth == 0: + return i + return len(text) + + +def scan_library(path): + done, todo = set(), set() + for source in path.rglob("*.cpp"): + text = source.read_text(errors="ignore") + for match in DEFINITION.finditer(text): + name = match.group(1) + if name.endswith("_nid_no_patch"): + continue + body = text[match.end() - 1:body_end(text, match.end() - 1)] + (todo if STUB in body else done).add(name) + todo -= done + return {"name": path.name, "label": path.name.removeprefix("libSce"), "done": len(done), "todo": len(todo)} + + +def summarize(groups): + done = sum(g["done"] for g in groups) + total = done + sum(g["todo"] for g in groups) + return {"done": done, "total": total, "percent": round(100 * done / total, 2) if total else 0, "groups": groups} + + +def collect_libraries(): + return summarize([scan_library(p) for p in sorted(PRX.iterdir()) if p.is_dir()]) + + +def camel(name): + return "".join(part.capitalize() for part in name.split("_")) + + +def collect_shaders(): + isa = {} + for line in ISA.read_text().splitlines(): + if line and not line.startswith("#"): + name, encoding = line.split() + isa[name] = encoding + by_camel = {camel(name): name for name in isa} + enum = re.search(r"enum class RdnaOpcode[^{]*\{(.*?)\};", OPCODES.read_text(), re.S).group(1) + opcodes = [o for o in re.findall(r"^\s*([A-Z]\w*)\s*[,=]", enum, re.M) if o not in OPCODE_SENTINELS] + supported, extra = set(), [] + for opcode in opcodes: + name = OPCODE_ALIASES.get(opcode) or by_camel.get(opcode) + if name in isa: + supported.add(name) + if name.startswith("FLAT_"): + supported.update(n for n in (s + name.removeprefix("FLAT_") for s in FLAT_SEGMENTS) if n in isa) + else: + extra.append(opcode) + groups = {} + for name, encoding in isa.items(): + group = groups.setdefault(encoding, {"name": encoding, "label": encoding, "done": 0, "todo": 0}) + group["done" if name in supported else "todo"] += 1 + result = summarize(sorted(groups.values(), key=lambda g: g["name"])) + result["extra"] = extra + return result + + +def worst_ratio(row, side): + area = sum(row) + return max(max(side * side * r / area ** 2, area ** 2 / (side * side * r)) for r in row) + + +def place(row, x, y, w, h, rects): + thickness = sum(row) / min(w, h) + offset = 0 + for area in row: + length = area / thickness + if w >= h: + rects.append((x, y + offset, thickness, length)) + else: + rects.append((x + offset, y, length, thickness)) + offset += length + return (x + thickness, y, w - thickness, h) if w >= h else (x, y + thickness, w, h - thickness) + + +def squarify(values, x, y, w, h): + total = sum(values) + areas = [v * w * h / total for v in values] + rects, row = [], [] + while areas: + side = min(w, h) + if not row or worst_ratio(row + [areas[0]], side) <= worst_ratio(row, side): + row.append(areas.pop(0)) + continue + x, y, w, h = place(row, x, y, w, h, rects) + row = [] + if row: + place(row, x, y, w, h, rects) + return rects + + +def cells(count, x, y, w, h): + if not count: + return [] + rows = max(1, min(count, round((count * h / w) ** 0.5))) + result = [] + for r in range(rows): + in_row = count // rows + (r < count % rows) + cw = w / in_row + result += [(x + c * cw, y + r * h / rows, cw, h / rows) for c in range(in_row)] + return result + + +def rect(x, y, w, h, color, stroke=0.5): + return (f'') + + +def text(x, y, value, size): + return (f'{escape(value)}') + + +def treemap(title, data, left): + groups = sorted((g for g in data["groups"] if g["done"] + g["todo"]), key=lambda g: -(g["done"] + g["todo"])) + parts = [text(left + 4, 21, f'{title}: {data["percent"]}% ({data["done"]}/{data["total"]})', 16)] + for group, (x, y, w, h) in zip(groups, squarify([g["done"] + g["todo"] for g in groups], left, HEADER, PANEL_WIDTH, MAP_HEIGHT)): + total = group["done"] + group["todo"] + parts.append(f'{escape(group["name"])}: {group["done"]}/{total} ({100 * group["done"] / total:.0f}%)') + for i, cell in enumerate(cells(total, x + 1, y + 1, w - 2, h - 2)): + parts.append(rect(*cell, DONE_COLOR if i < group["done"] else TODO_COLOR)) + parts.append(f'') + label = group["label"][:int((w - 10) / 7)] + if (label == group["label"] or len(label) >= 3) and h > 22: + parts.append(text(x + 5, y + 16, label, 12)) + parts.append("") + return parts + + +def render(libraries, shaders): + width, height = 2 * PANEL_WIDTH + GAP, HEADER + MAP_HEIGHT + parts = [f'', + rect(0, 0, width, height, BORDER, 0)] + parts += treemap("System libraries*", libraries, 0) + parts += treemap("GPU shader instructions", shaders, PANEL_WIDTH + GAP) + parts.append("") + return "\n".join(parts) + + +def badge(label, data): + percent = data["percent"] + color = "#4c1" if percent >= 90 else "#97ca00" if percent >= 60 else "#dfb317" if percent >= 30 else "#fe7d37" + value = f"{percent}%" + left, right = 10 + 7 * len(label), 10 + 7 * len(value) + width = left + right + return (f'' + f'' + f'' + f'{label}{value}') + + +def table(heading, column, data): + rows = [f"

{heading}

", "", + f""] + for group in sorted(data["groups"], key=lambda g: g["name"].lower()): + total = group["done"] + group["todo"] + percent = f'{100 * group["done"] / total:.0f}%' if total else "-" + rows.append(f'') + rows.append(f'') + rows.append("
{column}ImplementedTotal%
{escape(group["name"])}{group["done"]}{total}{percent}
Total{data["done"]}{data["total"]}{data["percent"]}%
") + return "\n".join(rows) + + +def summary(libraries, shaders): + extra = ", ".join(f"{escape(o)}" for o in shaders["extra"]) + return "\n".join([ + '', + '', + 'AnyPS5 progress', + '', + '', + "

Progress

", + 'progress', + f'

Generated by tools/progress.py on every push to main. ' + 'Raw numbers: progress.json.

', + table("System libraries", "Library", libraries), + "

A function is implemented when it no longer calls NotImplemented_nid_no_patch. " + f'The total only includes functions already declared in core/libs/prx, ' + "not every function exported by the PS5 firmware.

", + table("GPU shader instructions", "Encoding", shaders), + f'

The total is the AMD RDNA 1 + RDNA 2 instruction list (tools/rdna_isa.txt). ' + f'An instruction is implemented when the decoder recognizes it. ' + f"Decoded opcodes not present in AMD's public list are not counted: {extra}.

", + "", + ]) + "\n" + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument("output", type=Path) + output = parser.parse_args().output + output.mkdir(parents=True, exist_ok=True) + libraries, shaders = collect_libraries(), collect_shaders() + (output / "progress.json").write_text(json.dumps({"libraries": libraries, "shaders": shaders}, indent=2)) + (output / "badge-libraries.svg").write_text(badge("libraries*", libraries)) + (output / "badge-shaders.svg").write_text(badge("shaders", shaders)) + (output / "progress.svg").write_text(render(libraries, shaders)) + (output / "index.html").write_text(summary(libraries, shaders)) + print(f'libraries {libraries["done"]}/{libraries["total"]} ({libraries["percent"]}%)') + print(f'shaders {shaders["done"]}/{shaders["total"]} ({shaders["percent"]}%)') diff --git a/tools/rdna_isa.txt b/tools/rdna_isa.txt new file mode 100644 index 000000000..1d854a6c3 --- /dev/null +++ b/tools/rdna_isa.txt @@ -0,0 +1,1169 @@ +# AMD RDNA 1 + RDNA 2 instruction list (name, primary encoding). +# Source: AMD Machine-Readable GPU ISA Specification, https://gpuopen.com/machine-readable-isa/ +# Copyright (c) 2026 Advanced Micro Devices, Inc., or its affiliates. MIT License. +BUFFER_ATOMIC_ADD MUBUF +BUFFER_ATOMIC_ADD_X2 MUBUF +BUFFER_ATOMIC_AND MUBUF +BUFFER_ATOMIC_AND_X2 MUBUF +BUFFER_ATOMIC_CMPSWAP MUBUF +BUFFER_ATOMIC_CMPSWAP_X2 MUBUF +BUFFER_ATOMIC_CSUB MUBUF +BUFFER_ATOMIC_DEC MUBUF +BUFFER_ATOMIC_DEC_X2 MUBUF +BUFFER_ATOMIC_FCMPSWAP MUBUF +BUFFER_ATOMIC_FCMPSWAP_X2 MUBUF +BUFFER_ATOMIC_FMAX MUBUF +BUFFER_ATOMIC_FMAX_X2 MUBUF +BUFFER_ATOMIC_FMIN MUBUF +BUFFER_ATOMIC_FMIN_X2 MUBUF +BUFFER_ATOMIC_INC MUBUF +BUFFER_ATOMIC_INC_X2 MUBUF +BUFFER_ATOMIC_OR MUBUF +BUFFER_ATOMIC_OR_X2 MUBUF +BUFFER_ATOMIC_SMAX MUBUF +BUFFER_ATOMIC_SMAX_X2 MUBUF +BUFFER_ATOMIC_SMIN MUBUF +BUFFER_ATOMIC_SMIN_X2 MUBUF +BUFFER_ATOMIC_SUB MUBUF +BUFFER_ATOMIC_SUB_X2 MUBUF +BUFFER_ATOMIC_SWAP MUBUF +BUFFER_ATOMIC_SWAP_X2 MUBUF +BUFFER_ATOMIC_UMAX MUBUF +BUFFER_ATOMIC_UMAX_X2 MUBUF +BUFFER_ATOMIC_UMIN MUBUF +BUFFER_ATOMIC_UMIN_X2 MUBUF +BUFFER_ATOMIC_XOR MUBUF +BUFFER_ATOMIC_XOR_X2 MUBUF +BUFFER_GL0_INV MUBUF +BUFFER_GL1_INV MUBUF +BUFFER_LOAD_DWORD MUBUF +BUFFER_LOAD_DWORDX2 MUBUF +BUFFER_LOAD_DWORDX3 MUBUF +BUFFER_LOAD_DWORDX4 MUBUF +BUFFER_LOAD_FORMAT_D16_HI_X MUBUF +BUFFER_LOAD_FORMAT_D16_X MUBUF +BUFFER_LOAD_FORMAT_D16_XY MUBUF +BUFFER_LOAD_FORMAT_D16_XYZ MUBUF +BUFFER_LOAD_FORMAT_D16_XYZW MUBUF +BUFFER_LOAD_FORMAT_X MUBUF +BUFFER_LOAD_FORMAT_XY MUBUF +BUFFER_LOAD_FORMAT_XYZ MUBUF +BUFFER_LOAD_FORMAT_XYZW MUBUF +BUFFER_LOAD_SBYTE MUBUF +BUFFER_LOAD_SBYTE_D16 MUBUF +BUFFER_LOAD_SBYTE_D16_HI MUBUF +BUFFER_LOAD_SHORT_D16 MUBUF +BUFFER_LOAD_SHORT_D16_HI MUBUF +BUFFER_LOAD_SSHORT MUBUF +BUFFER_LOAD_UBYTE MUBUF +BUFFER_LOAD_UBYTE_D16 MUBUF +BUFFER_LOAD_UBYTE_D16_HI MUBUF +BUFFER_LOAD_USHORT MUBUF +BUFFER_STORE_BYTE MUBUF +BUFFER_STORE_BYTE_D16_HI MUBUF +BUFFER_STORE_DWORD MUBUF +BUFFER_STORE_DWORDX2 MUBUF +BUFFER_STORE_DWORDX3 MUBUF +BUFFER_STORE_DWORDX4 MUBUF +BUFFER_STORE_FORMAT_D16_HI_X MUBUF +BUFFER_STORE_FORMAT_D16_X MUBUF +BUFFER_STORE_FORMAT_D16_XY MUBUF +BUFFER_STORE_FORMAT_D16_XYZ MUBUF +BUFFER_STORE_FORMAT_D16_XYZW MUBUF +BUFFER_STORE_FORMAT_X MUBUF +BUFFER_STORE_FORMAT_XY MUBUF +BUFFER_STORE_FORMAT_XYZ MUBUF +BUFFER_STORE_FORMAT_XYZW MUBUF +BUFFER_STORE_SHORT MUBUF +BUFFER_STORE_SHORT_D16_HI MUBUF +DS_ADD_F32 DS +DS_ADD_RTN_F32 DS +DS_ADD_RTN_U32 DS +DS_ADD_RTN_U64 DS +DS_ADD_U32 DS +DS_ADD_U64 DS +DS_AND_B32 DS +DS_AND_B64 DS +DS_AND_RTN_B32 DS +DS_AND_RTN_B64 DS +DS_APPEND DS +DS_BPERMUTE_B32 DS +DS_CMPST_B32 DS +DS_CMPST_B64 DS +DS_CMPST_F32 DS +DS_CMPST_F64 DS +DS_CMPST_RTN_B32 DS +DS_CMPST_RTN_B64 DS +DS_CMPST_RTN_F32 DS +DS_CMPST_RTN_F64 DS +DS_CONDXCHG32_RTN_B64 DS +DS_CONSUME DS +DS_DEC_RTN_U32 DS +DS_DEC_RTN_U64 DS +DS_DEC_U32 DS +DS_DEC_U64 DS +DS_GWS_BARRIER DS +DS_GWS_INIT DS +DS_GWS_SEMA_BR DS +DS_GWS_SEMA_P DS +DS_GWS_SEMA_RELEASE_ALL DS +DS_GWS_SEMA_V DS +DS_INC_RTN_U32 DS +DS_INC_RTN_U64 DS +DS_INC_U32 DS +DS_INC_U64 DS +DS_MAX_F32 DS +DS_MAX_F64 DS +DS_MAX_I32 DS +DS_MAX_I64 DS +DS_MAX_RTN_F32 DS +DS_MAX_RTN_F64 DS +DS_MAX_RTN_I32 DS +DS_MAX_RTN_I64 DS +DS_MAX_RTN_U32 DS +DS_MAX_RTN_U64 DS +DS_MAX_U32 DS +DS_MAX_U64 DS +DS_MIN_F32 DS +DS_MIN_F64 DS +DS_MIN_I32 DS +DS_MIN_I64 DS +DS_MIN_RTN_F32 DS +DS_MIN_RTN_F64 DS +DS_MIN_RTN_I32 DS +DS_MIN_RTN_I64 DS +DS_MIN_RTN_U32 DS +DS_MIN_RTN_U64 DS +DS_MIN_U32 DS +DS_MIN_U64 DS +DS_MSKOR_B32 DS +DS_MSKOR_B64 DS +DS_MSKOR_RTN_B32 DS +DS_MSKOR_RTN_B64 DS +DS_NOP DS +DS_ORDERED_COUNT DS +DS_OR_B32 DS +DS_OR_B64 DS +DS_OR_RTN_B32 DS +DS_OR_RTN_B64 DS +DS_PERMUTE_B32 DS +DS_READ2ST64_B32 DS +DS_READ2ST64_B64 DS +DS_READ2_B32 DS +DS_READ2_B64 DS +DS_READ_ADDTID_B32 DS +DS_READ_B128 DS +DS_READ_B32 DS +DS_READ_B64 DS +DS_READ_B96 DS +DS_READ_I16 DS +DS_READ_I8 DS +DS_READ_I8_D16 DS +DS_READ_I8_D16_HI DS +DS_READ_U16 DS +DS_READ_U16_D16 DS +DS_READ_U16_D16_HI DS +DS_READ_U8 DS +DS_READ_U8_D16 DS +DS_READ_U8_D16_HI DS +DS_RSUB_RTN_U32 DS +DS_RSUB_RTN_U64 DS +DS_RSUB_U32 DS +DS_RSUB_U64 DS +DS_SUB_RTN_U32 DS +DS_SUB_RTN_U64 DS +DS_SUB_U32 DS +DS_SUB_U64 DS +DS_SWIZZLE_B32 DS +DS_WRAP_RTN_B32 DS +DS_WRITE2ST64_B32 DS +DS_WRITE2ST64_B64 DS +DS_WRITE2_B32 DS +DS_WRITE2_B64 DS +DS_WRITE_ADDTID_B32 DS +DS_WRITE_B128 DS +DS_WRITE_B16 DS +DS_WRITE_B16_D16_HI DS +DS_WRITE_B32 DS +DS_WRITE_B64 DS +DS_WRITE_B8 DS +DS_WRITE_B8_D16_HI DS +DS_WRITE_B96 DS +DS_WRXCHG2ST64_RTN_B32 DS +DS_WRXCHG2ST64_RTN_B64 DS +DS_WRXCHG2_RTN_B32 DS +DS_WRXCHG2_RTN_B64 DS +DS_WRXCHG_RTN_B32 DS +DS_WRXCHG_RTN_B64 DS +DS_XOR_B32 DS +DS_XOR_B64 DS +DS_XOR_RTN_B32 DS +DS_XOR_RTN_B64 DS +EXP EXP +FLAT_ATOMIC_ADD FLAT +FLAT_ATOMIC_ADD_X2 FLAT +FLAT_ATOMIC_AND FLAT +FLAT_ATOMIC_AND_X2 FLAT +FLAT_ATOMIC_CMPSWAP FLAT +FLAT_ATOMIC_CMPSWAP_X2 FLAT +FLAT_ATOMIC_DEC FLAT +FLAT_ATOMIC_DEC_X2 FLAT +FLAT_ATOMIC_FCMPSWAP FLAT +FLAT_ATOMIC_FCMPSWAP_X2 FLAT +FLAT_ATOMIC_FMAX FLAT +FLAT_ATOMIC_FMAX_X2 FLAT +FLAT_ATOMIC_FMIN FLAT +FLAT_ATOMIC_FMIN_X2 FLAT +FLAT_ATOMIC_INC FLAT +FLAT_ATOMIC_INC_X2 FLAT +FLAT_ATOMIC_OR FLAT +FLAT_ATOMIC_OR_X2 FLAT +FLAT_ATOMIC_SMAX FLAT +FLAT_ATOMIC_SMAX_X2 FLAT +FLAT_ATOMIC_SMIN FLAT +FLAT_ATOMIC_SMIN_X2 FLAT +FLAT_ATOMIC_SUB FLAT +FLAT_ATOMIC_SUB_X2 FLAT +FLAT_ATOMIC_SWAP FLAT +FLAT_ATOMIC_SWAP_X2 FLAT +FLAT_ATOMIC_UMAX FLAT +FLAT_ATOMIC_UMAX_X2 FLAT +FLAT_ATOMIC_UMIN FLAT +FLAT_ATOMIC_UMIN_X2 FLAT +FLAT_ATOMIC_XOR FLAT +FLAT_ATOMIC_XOR_X2 FLAT +FLAT_LOAD_DWORD FLAT +FLAT_LOAD_DWORDX2 FLAT +FLAT_LOAD_DWORDX3 FLAT +FLAT_LOAD_DWORDX4 FLAT +FLAT_LOAD_SBYTE FLAT +FLAT_LOAD_SBYTE_D16 FLAT +FLAT_LOAD_SBYTE_D16_HI FLAT +FLAT_LOAD_SHORT_D16 FLAT +FLAT_LOAD_SHORT_D16_HI FLAT +FLAT_LOAD_SSHORT FLAT +FLAT_LOAD_UBYTE FLAT +FLAT_LOAD_UBYTE_D16 FLAT +FLAT_LOAD_UBYTE_D16_HI FLAT +FLAT_LOAD_USHORT FLAT +FLAT_STORE_BYTE FLAT +FLAT_STORE_BYTE_D16_HI FLAT +FLAT_STORE_DWORD FLAT +FLAT_STORE_DWORDX2 FLAT +FLAT_STORE_DWORDX3 FLAT +FLAT_STORE_DWORDX4 FLAT +FLAT_STORE_SHORT FLAT +FLAT_STORE_SHORT_D16_HI FLAT +GLOBAL_ATOMIC_ADD GLOBAL +GLOBAL_ATOMIC_ADD_X2 GLOBAL +GLOBAL_ATOMIC_AND GLOBAL +GLOBAL_ATOMIC_AND_X2 GLOBAL +GLOBAL_ATOMIC_CMPSWAP GLOBAL +GLOBAL_ATOMIC_CMPSWAP_X2 GLOBAL +GLOBAL_ATOMIC_CSUB GLOBAL +GLOBAL_ATOMIC_DEC GLOBAL +GLOBAL_ATOMIC_DEC_X2 GLOBAL +GLOBAL_ATOMIC_FCMPSWAP GLOBAL +GLOBAL_ATOMIC_FCMPSWAP_X2 GLOBAL +GLOBAL_ATOMIC_FMAX GLOBAL +GLOBAL_ATOMIC_FMAX_X2 GLOBAL +GLOBAL_ATOMIC_FMIN GLOBAL +GLOBAL_ATOMIC_FMIN_X2 GLOBAL +GLOBAL_ATOMIC_INC GLOBAL +GLOBAL_ATOMIC_INC_X2 GLOBAL +GLOBAL_ATOMIC_OR GLOBAL +GLOBAL_ATOMIC_OR_X2 GLOBAL +GLOBAL_ATOMIC_SMAX GLOBAL +GLOBAL_ATOMIC_SMAX_X2 GLOBAL +GLOBAL_ATOMIC_SMIN GLOBAL +GLOBAL_ATOMIC_SMIN_X2 GLOBAL +GLOBAL_ATOMIC_SUB GLOBAL +GLOBAL_ATOMIC_SUB_X2 GLOBAL +GLOBAL_ATOMIC_SWAP GLOBAL +GLOBAL_ATOMIC_SWAP_X2 GLOBAL +GLOBAL_ATOMIC_UMAX GLOBAL +GLOBAL_ATOMIC_UMAX_X2 GLOBAL +GLOBAL_ATOMIC_UMIN GLOBAL +GLOBAL_ATOMIC_UMIN_X2 GLOBAL +GLOBAL_ATOMIC_XOR GLOBAL +GLOBAL_ATOMIC_XOR_X2 GLOBAL +GLOBAL_LOAD_DWORD GLOBAL +GLOBAL_LOAD_DWORDX2 GLOBAL +GLOBAL_LOAD_DWORDX3 GLOBAL +GLOBAL_LOAD_DWORDX4 GLOBAL +GLOBAL_LOAD_DWORD_ADDTID GLOBAL +GLOBAL_LOAD_SBYTE GLOBAL +GLOBAL_LOAD_SBYTE_D16 GLOBAL +GLOBAL_LOAD_SBYTE_D16_HI GLOBAL +GLOBAL_LOAD_SHORT_D16 GLOBAL +GLOBAL_LOAD_SHORT_D16_HI GLOBAL +GLOBAL_LOAD_SSHORT GLOBAL +GLOBAL_LOAD_UBYTE GLOBAL +GLOBAL_LOAD_UBYTE_D16 GLOBAL +GLOBAL_LOAD_UBYTE_D16_HI GLOBAL +GLOBAL_LOAD_USHORT GLOBAL +GLOBAL_STORE_BYTE GLOBAL +GLOBAL_STORE_BYTE_D16_HI GLOBAL +GLOBAL_STORE_DWORD GLOBAL +GLOBAL_STORE_DWORDX2 GLOBAL +GLOBAL_STORE_DWORDX3 GLOBAL +GLOBAL_STORE_DWORDX4 GLOBAL +GLOBAL_STORE_DWORD_ADDTID GLOBAL +GLOBAL_STORE_SHORT GLOBAL +GLOBAL_STORE_SHORT_D16_HI GLOBAL +IMAGE_ATOMIC_ADD MIMG +IMAGE_ATOMIC_AND MIMG +IMAGE_ATOMIC_CMPSWAP MIMG +IMAGE_ATOMIC_DEC MIMG +IMAGE_ATOMIC_FCMPSWAP MIMG +IMAGE_ATOMIC_FMAX MIMG +IMAGE_ATOMIC_FMIN MIMG +IMAGE_ATOMIC_INC MIMG +IMAGE_ATOMIC_OR MIMG +IMAGE_ATOMIC_SMAX MIMG +IMAGE_ATOMIC_SMIN MIMG +IMAGE_ATOMIC_SUB MIMG +IMAGE_ATOMIC_SWAP MIMG +IMAGE_ATOMIC_UMAX MIMG +IMAGE_ATOMIC_UMIN MIMG +IMAGE_ATOMIC_XOR MIMG +IMAGE_BVH64_INTERSECT_RAY MIMG +IMAGE_BVH_INTERSECT_RAY MIMG +IMAGE_GATHER4 MIMG +IMAGE_GATHER4H MIMG +IMAGE_GATHER4H_PCK MIMG +IMAGE_GATHER4_B MIMG +IMAGE_GATHER4_B_CL MIMG +IMAGE_GATHER4_B_CL_O MIMG +IMAGE_GATHER4_B_O MIMG +IMAGE_GATHER4_C MIMG +IMAGE_GATHER4_CL MIMG +IMAGE_GATHER4_CL_O MIMG +IMAGE_GATHER4_C_B MIMG +IMAGE_GATHER4_C_B_CL MIMG +IMAGE_GATHER4_C_B_CL_O MIMG +IMAGE_GATHER4_C_B_O MIMG +IMAGE_GATHER4_C_CL MIMG +IMAGE_GATHER4_C_CL_O MIMG +IMAGE_GATHER4_C_L MIMG +IMAGE_GATHER4_C_LZ MIMG +IMAGE_GATHER4_C_LZ_O MIMG +IMAGE_GATHER4_C_L_O MIMG +IMAGE_GATHER4_C_O MIMG +IMAGE_GATHER4_L MIMG +IMAGE_GATHER4_LZ MIMG +IMAGE_GATHER4_LZ_O MIMG +IMAGE_GATHER4_L_O MIMG +IMAGE_GATHER4_O MIMG +IMAGE_GATHER8H_PCK MIMG +IMAGE_GET_LOD MIMG +IMAGE_GET_RESINFO MIMG +IMAGE_LOAD MIMG +IMAGE_LOAD_BY2 MIMG +IMAGE_LOAD_BY4 MIMG +IMAGE_LOAD_MIP MIMG +IMAGE_LOAD_MIP_BY2 MIMG +IMAGE_LOAD_MIP_BY4 MIMG +IMAGE_LOAD_MIP_PCK MIMG +IMAGE_LOAD_MIP_PCK2 MIMG +IMAGE_LOAD_MIP_PCK4 MIMG +IMAGE_LOAD_MIP_PCK_SGN MIMG +IMAGE_LOAD_PCK MIMG +IMAGE_LOAD_PCK2 MIMG +IMAGE_LOAD_PCK4 MIMG +IMAGE_LOAD_PCK_SGN MIMG +IMAGE_MSAA_LOAD MIMG +IMAGE_SAMPLE MIMG +IMAGE_SAMPLE_B MIMG +IMAGE_SAMPLE_B_CL MIMG +IMAGE_SAMPLE_B_CL_O MIMG +IMAGE_SAMPLE_B_O MIMG +IMAGE_SAMPLE_C MIMG +IMAGE_SAMPLE_CD MIMG +IMAGE_SAMPLE_CD_CL MIMG +IMAGE_SAMPLE_CD_CL_G16 MIMG +IMAGE_SAMPLE_CD_CL_O MIMG +IMAGE_SAMPLE_CD_CL_O_G16 MIMG +IMAGE_SAMPLE_CD_G16 MIMG +IMAGE_SAMPLE_CD_O MIMG +IMAGE_SAMPLE_CD_O_G16 MIMG +IMAGE_SAMPLE_CL MIMG +IMAGE_SAMPLE_CL_O MIMG +IMAGE_SAMPLE_C_B MIMG +IMAGE_SAMPLE_C_B_CL MIMG +IMAGE_SAMPLE_C_B_CL_O MIMG +IMAGE_SAMPLE_C_B_O MIMG +IMAGE_SAMPLE_C_CD MIMG +IMAGE_SAMPLE_C_CD_CL MIMG +IMAGE_SAMPLE_C_CD_CL_G16 MIMG +IMAGE_SAMPLE_C_CD_CL_O MIMG +IMAGE_SAMPLE_C_CD_CL_O_G16 MIMG +IMAGE_SAMPLE_C_CD_G16 MIMG +IMAGE_SAMPLE_C_CD_O MIMG +IMAGE_SAMPLE_C_CD_O_G16 MIMG +IMAGE_SAMPLE_C_CL MIMG +IMAGE_SAMPLE_C_CL_O MIMG +IMAGE_SAMPLE_C_D MIMG +IMAGE_SAMPLE_C_D_CL MIMG +IMAGE_SAMPLE_C_D_CL_G16 MIMG +IMAGE_SAMPLE_C_D_CL_O MIMG +IMAGE_SAMPLE_C_D_CL_O_G16 MIMG +IMAGE_SAMPLE_C_D_G16 MIMG +IMAGE_SAMPLE_C_D_O MIMG +IMAGE_SAMPLE_C_D_O_G16 MIMG +IMAGE_SAMPLE_C_L MIMG +IMAGE_SAMPLE_C_LZ MIMG +IMAGE_SAMPLE_C_LZ_O MIMG +IMAGE_SAMPLE_C_L_O MIMG +IMAGE_SAMPLE_C_O MIMG +IMAGE_SAMPLE_D MIMG +IMAGE_SAMPLE_D_CL MIMG +IMAGE_SAMPLE_D_CL_G16 MIMG +IMAGE_SAMPLE_D_CL_O MIMG +IMAGE_SAMPLE_D_CL_O_G16 MIMG +IMAGE_SAMPLE_D_G16 MIMG +IMAGE_SAMPLE_D_O MIMG +IMAGE_SAMPLE_D_O_G16 MIMG +IMAGE_SAMPLE_L MIMG +IMAGE_SAMPLE_LZ MIMG +IMAGE_SAMPLE_LZ_O MIMG +IMAGE_SAMPLE_L_O MIMG +IMAGE_SAMPLE_O MIMG +IMAGE_STORE MIMG +IMAGE_STORE_BY2 MIMG +IMAGE_STORE_BY4 MIMG +IMAGE_STORE_MIP MIMG +IMAGE_STORE_MIP_BY2 MIMG +IMAGE_STORE_MIP_BY4 MIMG +IMAGE_STORE_MIP_PCK MIMG +IMAGE_STORE_MIP_PCK2 MIMG +IMAGE_STORE_MIP_PCK4 MIMG +IMAGE_STORE_PCK MIMG +IMAGE_STORE_PCK2 MIMG +IMAGE_STORE_PCK4 MIMG +SCRATCH_LOAD_DWORD SCRATCH +SCRATCH_LOAD_DWORDX2 SCRATCH +SCRATCH_LOAD_DWORDX3 SCRATCH +SCRATCH_LOAD_DWORDX4 SCRATCH +SCRATCH_LOAD_SBYTE SCRATCH +SCRATCH_LOAD_SBYTE_D16 SCRATCH +SCRATCH_LOAD_SBYTE_D16_HI SCRATCH +SCRATCH_LOAD_SHORT_D16 SCRATCH +SCRATCH_LOAD_SHORT_D16_HI SCRATCH +SCRATCH_LOAD_SSHORT SCRATCH +SCRATCH_LOAD_UBYTE SCRATCH +SCRATCH_LOAD_UBYTE_D16 SCRATCH +SCRATCH_LOAD_UBYTE_D16_HI SCRATCH +SCRATCH_LOAD_USHORT SCRATCH +SCRATCH_STORE_BYTE SCRATCH +SCRATCH_STORE_BYTE_D16_HI SCRATCH +SCRATCH_STORE_DWORD SCRATCH +SCRATCH_STORE_DWORDX2 SCRATCH +SCRATCH_STORE_DWORDX3 SCRATCH +SCRATCH_STORE_DWORDX4 SCRATCH +SCRATCH_STORE_SHORT SCRATCH +SCRATCH_STORE_SHORT_D16_HI SCRATCH +S_ABSDIFF_I32 SOP2 +S_ABS_I32 SOP1 +S_ADDC_U32 SOP2 +S_ADDK_I32 SOPK +S_ADD_I32 SOP2 +S_ADD_U32 SOP2 +S_ANDN1_SAVEEXEC_B32 SOP1 +S_ANDN1_SAVEEXEC_B64 SOP1 +S_ANDN1_WREXEC_B32 SOP1 +S_ANDN1_WREXEC_B64 SOP1 +S_ANDN2_B32 SOP2 +S_ANDN2_B64 SOP2 +S_ANDN2_SAVEEXEC_B32 SOP1 +S_ANDN2_SAVEEXEC_B64 SOP1 +S_ANDN2_WREXEC_B32 SOP1 +S_ANDN2_WREXEC_B64 SOP1 +S_AND_B32 SOP2 +S_AND_B64 SOP2 +S_AND_SAVEEXEC_B32 SOP1 +S_AND_SAVEEXEC_B64 SOP1 +S_ASHR_I32 SOP2 +S_ASHR_I64 SOP2 +S_ATC_PROBE SMEM +S_ATC_PROBE_BUFFER SMEM +S_BARRIER SOPP +S_BCNT0_I32_B32 SOP1 +S_BCNT0_I32_B64 SOP1 +S_BCNT1_I32_B32 SOP1 +S_BCNT1_I32_B64 SOP1 +S_BFE_I32 SOP2 +S_BFE_I64 SOP2 +S_BFE_U32 SOP2 +S_BFE_U64 SOP2 +S_BFM_B32 SOP2 +S_BFM_B64 SOP2 +S_BITCMP0_B32 SOPC +S_BITCMP0_B64 SOPC +S_BITCMP1_B32 SOPC +S_BITCMP1_B64 SOPC +S_BITREPLICATE_B64_B32 SOP1 +S_BITSET0_B32 SOP1 +S_BITSET0_B64 SOP1 +S_BITSET1_B32 SOP1 +S_BITSET1_B64 SOP1 +S_BRANCH SOPP +S_BREV_B32 SOP1 +S_BREV_B64 SOP1 +S_BUFFER_LOAD_DWORD SMEM +S_BUFFER_LOAD_DWORDX16 SMEM +S_BUFFER_LOAD_DWORDX2 SMEM +S_BUFFER_LOAD_DWORDX4 SMEM +S_BUFFER_LOAD_DWORDX8 SMEM +S_CALL_B64 SOPK +S_CBRANCH_CDBGSYS SOPP +S_CBRANCH_CDBGSYS_AND_USER SOPP +S_CBRANCH_CDBGSYS_OR_USER SOPP +S_CBRANCH_CDBGUSER SOPP +S_CBRANCH_EXECNZ SOPP +S_CBRANCH_EXECZ SOPP +S_CBRANCH_SCC0 SOPP +S_CBRANCH_SCC1 SOPP +S_CBRANCH_VCCNZ SOPP +S_CBRANCH_VCCZ SOPP +S_CLAUSE SOPP +S_CMOVK_I32 SOPK +S_CMOV_B32 SOP1 +S_CMOV_B64 SOP1 +S_CMPK_EQ_I32 SOPK +S_CMPK_EQ_U32 SOPK +S_CMPK_GE_I32 SOPK +S_CMPK_GE_U32 SOPK +S_CMPK_GT_I32 SOPK +S_CMPK_GT_U32 SOPK +S_CMPK_LE_I32 SOPK +S_CMPK_LE_U32 SOPK +S_CMPK_LG_I32 SOPK +S_CMPK_LG_U32 SOPK +S_CMPK_LT_I32 SOPK +S_CMPK_LT_U32 SOPK +S_CMP_EQ_I32 SOPC +S_CMP_EQ_U32 SOPC +S_CMP_EQ_U64 SOPC +S_CMP_GE_I32 SOPC +S_CMP_GE_U32 SOPC +S_CMP_GT_I32 SOPC +S_CMP_GT_U32 SOPC +S_CMP_LE_I32 SOPC +S_CMP_LE_U32 SOPC +S_CMP_LG_I32 SOPC +S_CMP_LG_U32 SOPC +S_CMP_LG_U64 SOPC +S_CMP_LT_I32 SOPC +S_CMP_LT_U32 SOPC +S_CODE_END SOPP +S_CSELECT_B32 SOP2 +S_CSELECT_B64 SOP2 +S_DCACHE_INV SMEM +S_DECPERFLEVEL SOPP +S_DENORM_MODE SOPP +S_ENDPGM SOPP +S_ENDPGM_ORDERED_PS_DONE SOPP +S_ENDPGM_SAVED SOPP +S_FF0_I32_B32 SOP1 +S_FF0_I32_B64 SOP1 +S_FF1_I32_B32 SOP1 +S_FF1_I32_B64 SOP1 +S_FLBIT_I32 SOP1 +S_FLBIT_I32_B32 SOP1 +S_FLBIT_I32_B64 SOP1 +S_FLBIT_I32_I64 SOP1 +S_GETPC_B64 SOP1 +S_GETREG_B32 SOPK +S_GET_WAVEID_IN_WORKGROUP SMEM +S_GL1_INV SMEM +S_ICACHE_INV SOPP +S_INCPERFLEVEL SOPP +S_INST_PREFETCH SOPP +S_LOAD_DWORD SMEM +S_LOAD_DWORDX16 SMEM +S_LOAD_DWORDX2 SMEM +S_LOAD_DWORDX4 SMEM +S_LOAD_DWORDX8 SMEM +S_LSHL1_ADD_U32 SOP2 +S_LSHL2_ADD_U32 SOP2 +S_LSHL3_ADD_U32 SOP2 +S_LSHL4_ADD_U32 SOP2 +S_LSHL_B32 SOP2 +S_LSHL_B64 SOP2 +S_LSHR_B32 SOP2 +S_LSHR_B64 SOP2 +S_MAX_I32 SOP2 +S_MAX_U32 SOP2 +S_MEMREALTIME SMEM +S_MEMTIME SMEM +S_MIN_I32 SOP2 +S_MIN_U32 SOP2 +S_MOVK_I32 SOPK +S_MOVRELD_B32 SOP1 +S_MOVRELD_B64 SOP1 +S_MOVRELSD_2_B32 SOP1 +S_MOVRELS_B32 SOP1 +S_MOVRELS_B64 SOP1 +S_MOV_B32 SOP1 +S_MOV_B64 SOP1 +S_MULK_I32 SOPK +S_MUL_HI_I32 SOP2 +S_MUL_HI_U32 SOP2 +S_MUL_I32 SOP2 +S_NAND_B32 SOP2 +S_NAND_B64 SOP2 +S_NAND_SAVEEXEC_B32 SOP1 +S_NAND_SAVEEXEC_B64 SOP1 +S_NOP SOPP +S_NOR_B32 SOP2 +S_NOR_B64 SOP2 +S_NOR_SAVEEXEC_B32 SOP1 +S_NOR_SAVEEXEC_B64 SOP1 +S_NOT_B32 SOP1 +S_NOT_B64 SOP1 +S_ORN1_SAVEEXEC_B32 SOP1 +S_ORN1_SAVEEXEC_B64 SOP1 +S_ORN2_B32 SOP2 +S_ORN2_B64 SOP2 +S_ORN2_SAVEEXEC_B32 SOP1 +S_ORN2_SAVEEXEC_B64 SOP1 +S_OR_B32 SOP2 +S_OR_B64 SOP2 +S_OR_SAVEEXEC_B32 SOP1 +S_OR_SAVEEXEC_B64 SOP1 +S_PACK_HH_B32_B16 SOP2 +S_PACK_LH_B32_B16 SOP2 +S_PACK_LL_B32_B16 SOP2 +S_QUADMASK_B32 SOP1 +S_QUADMASK_B64 SOP1 +S_RFE_B64 SOP1 +S_ROUND_MODE SOPP +S_SCRATCH_LOAD_DWORD SMEM +S_SCRATCH_LOAD_DWORDX2 SMEM +S_SCRATCH_LOAD_DWORDX4 SMEM +S_SENDMSG SOPP +S_SENDMSGHALT SOPP +S_SETHALT SOPP +S_SETKILL SOPP +S_SETPC_B64 SOP1 +S_SETPRIO SOPP +S_SETREG_B32 SOPK +S_SETREG_IMM32_B32 SOPK +S_SEXT_I32_I16 SOP1 +S_SEXT_I32_I8 SOP1 +S_SLEEP SOPP +S_SUBB_U32 SOP2 +S_SUBVECTOR_LOOP_BEGIN SOPK +S_SUBVECTOR_LOOP_END SOPK +S_SUB_I32 SOP2 +S_SUB_U32 SOP2 +S_SWAPPC_B64 SOP1 +S_TRAP SOPP +S_TTRACEDATA SOPP +S_TTRACEDATA_IMM SOPP +S_VERSION SOPK +S_WAITCNT SOPP +S_WAITCNT_DEPCTR SOPP +S_WAITCNT_EXPCNT SOPK +S_WAITCNT_LGKMCNT SOPK +S_WAITCNT_VMCNT SOPK +S_WAITCNT_VSCNT SOPK +S_WAIT_IDLE SOPP +S_WAKEUP SOPP +S_WQM_B32 SOP1 +S_WQM_B64 SOP1 +S_XNOR_B32 SOP2 +S_XNOR_B64 SOP2 +S_XNOR_SAVEEXEC_B32 SOP1 +S_XNOR_SAVEEXEC_B64 SOP1 +S_XOR_B32 SOP2 +S_XOR_B64 SOP2 +S_XOR_SAVEEXEC_B32 SOP1 +S_XOR_SAVEEXEC_B64 SOP1 +TBUFFER_LOAD_FORMAT_D16_X MTBUF +TBUFFER_LOAD_FORMAT_D16_XY MTBUF +TBUFFER_LOAD_FORMAT_D16_XYZ MTBUF +TBUFFER_LOAD_FORMAT_D16_XYZW MTBUF +TBUFFER_LOAD_FORMAT_X MTBUF +TBUFFER_LOAD_FORMAT_XY MTBUF +TBUFFER_LOAD_FORMAT_XYZ MTBUF +TBUFFER_LOAD_FORMAT_XYZW MTBUF +TBUFFER_STORE_FORMAT_D16_X MTBUF +TBUFFER_STORE_FORMAT_D16_XY MTBUF +TBUFFER_STORE_FORMAT_D16_XYZ MTBUF +TBUFFER_STORE_FORMAT_D16_XYZW MTBUF +TBUFFER_STORE_FORMAT_X MTBUF +TBUFFER_STORE_FORMAT_XY MTBUF +TBUFFER_STORE_FORMAT_XYZ MTBUF +TBUFFER_STORE_FORMAT_XYZW MTBUF +V_ADD3_U32 VOP3 +V_ADD_CO_CI_U32 VOP2 +V_ADD_CO_U32 VOP3 +V_ADD_F16 VOP2 +V_ADD_F32 VOP2 +V_ADD_F64 VOP3 +V_ADD_LSHL_U32 VOP3 +V_ADD_NC_I16 VOP3 +V_ADD_NC_I32 VOP3 +V_ADD_NC_U16 VOP3 +V_ADD_NC_U32 VOP2 +V_ALIGNBIT_B32 VOP3 +V_ALIGNBYTE_B32 VOP3 +V_AND_B32 VOP2 +V_AND_OR_B32 VOP3 +V_ASHRREV_I16 VOP3 +V_ASHRREV_I32 VOP2 +V_ASHRREV_I64 VOP3 +V_BCNT_U32_B32 VOP3 +V_BFE_I32 VOP3 +V_BFE_U32 VOP3 +V_BFI_B32 VOP3 +V_BFM_B32 VOP3 +V_BFREV_B32 VOP1 +V_CEIL_F16 VOP1 +V_CEIL_F32 VOP1 +V_CEIL_F64 VOP1 +V_CLREXCP VOP1 +V_CMPX_CLASS_F16 VOPC +V_CMPX_CLASS_F32 VOPC +V_CMPX_CLASS_F64 VOPC +V_CMPX_EQ_F16 VOPC +V_CMPX_EQ_F32 VOPC +V_CMPX_EQ_F64 VOPC +V_CMPX_EQ_I16 VOPC +V_CMPX_EQ_I32 VOPC +V_CMPX_EQ_I64 VOPC +V_CMPX_EQ_U16 VOPC +V_CMPX_EQ_U32 VOPC +V_CMPX_EQ_U64 VOPC +V_CMPX_F_F16 VOPC +V_CMPX_F_F32 VOPC +V_CMPX_F_F64 VOPC +V_CMPX_F_I32 VOPC +V_CMPX_F_I64 VOPC +V_CMPX_F_U32 VOPC +V_CMPX_F_U64 VOPC +V_CMPX_GE_F16 VOPC +V_CMPX_GE_F32 VOPC +V_CMPX_GE_F64 VOPC +V_CMPX_GE_I16 VOPC +V_CMPX_GE_I32 VOPC +V_CMPX_GE_I64 VOPC +V_CMPX_GE_U16 VOPC +V_CMPX_GE_U32 VOPC +V_CMPX_GE_U64 VOPC +V_CMPX_GT_F16 VOPC +V_CMPX_GT_F32 VOPC +V_CMPX_GT_F64 VOPC +V_CMPX_GT_I16 VOPC +V_CMPX_GT_I32 VOPC +V_CMPX_GT_I64 VOPC +V_CMPX_GT_U16 VOPC +V_CMPX_GT_U32 VOPC +V_CMPX_GT_U64 VOPC +V_CMPX_LE_F16 VOPC +V_CMPX_LE_F32 VOPC +V_CMPX_LE_F64 VOPC +V_CMPX_LE_I16 VOPC +V_CMPX_LE_I32 VOPC +V_CMPX_LE_I64 VOPC +V_CMPX_LE_U16 VOPC +V_CMPX_LE_U32 VOPC +V_CMPX_LE_U64 VOPC +V_CMPX_LG_F16 VOPC +V_CMPX_LG_F32 VOPC +V_CMPX_LG_F64 VOPC +V_CMPX_LT_F16 VOPC +V_CMPX_LT_F32 VOPC +V_CMPX_LT_F64 VOPC +V_CMPX_LT_I16 VOPC +V_CMPX_LT_I32 VOPC +V_CMPX_LT_I64 VOPC +V_CMPX_LT_U16 VOPC +V_CMPX_LT_U32 VOPC +V_CMPX_LT_U64 VOPC +V_CMPX_NEQ_F16 VOPC +V_CMPX_NEQ_F32 VOPC +V_CMPX_NEQ_F64 VOPC +V_CMPX_NE_I16 VOPC +V_CMPX_NE_I32 VOPC +V_CMPX_NE_I64 VOPC +V_CMPX_NE_U16 VOPC +V_CMPX_NE_U32 VOPC +V_CMPX_NE_U64 VOPC +V_CMPX_NGE_F16 VOPC +V_CMPX_NGE_F32 VOPC +V_CMPX_NGE_F64 VOPC +V_CMPX_NGT_F16 VOPC +V_CMPX_NGT_F32 VOPC +V_CMPX_NGT_F64 VOPC +V_CMPX_NLE_F16 VOPC +V_CMPX_NLE_F32 VOPC +V_CMPX_NLE_F64 VOPC +V_CMPX_NLG_F16 VOPC +V_CMPX_NLG_F32 VOPC +V_CMPX_NLG_F64 VOPC +V_CMPX_NLT_F16 VOPC +V_CMPX_NLT_F32 VOPC +V_CMPX_NLT_F64 VOPC +V_CMPX_O_F16 VOPC +V_CMPX_O_F32 VOPC +V_CMPX_O_F64 VOPC +V_CMPX_TRU_F16 VOPC +V_CMPX_TRU_F32 VOPC +V_CMPX_TRU_F64 VOPC +V_CMPX_T_I32 VOPC +V_CMPX_T_I64 VOPC +V_CMPX_T_U32 VOPC +V_CMPX_T_U64 VOPC +V_CMPX_U_F16 VOPC +V_CMPX_U_F32 VOPC +V_CMPX_U_F64 VOPC +V_CMP_CLASS_F16 VOPC +V_CMP_CLASS_F32 VOPC +V_CMP_CLASS_F64 VOPC +V_CMP_EQ_F16 VOPC +V_CMP_EQ_F32 VOPC +V_CMP_EQ_F64 VOPC +V_CMP_EQ_I16 VOPC +V_CMP_EQ_I32 VOPC +V_CMP_EQ_I64 VOPC +V_CMP_EQ_U16 VOPC +V_CMP_EQ_U32 VOPC +V_CMP_EQ_U64 VOPC +V_CMP_F_F16 VOPC +V_CMP_F_F32 VOPC +V_CMP_F_F64 VOPC +V_CMP_F_I32 VOPC +V_CMP_F_I64 VOPC +V_CMP_F_U32 VOPC +V_CMP_F_U64 VOPC +V_CMP_GE_F16 VOPC +V_CMP_GE_F32 VOPC +V_CMP_GE_F64 VOPC +V_CMP_GE_I16 VOPC +V_CMP_GE_I32 VOPC +V_CMP_GE_I64 VOPC +V_CMP_GE_U16 VOPC +V_CMP_GE_U32 VOPC +V_CMP_GE_U64 VOPC +V_CMP_GT_F16 VOPC +V_CMP_GT_F32 VOPC +V_CMP_GT_F64 VOPC +V_CMP_GT_I16 VOPC +V_CMP_GT_I32 VOPC +V_CMP_GT_I64 VOPC +V_CMP_GT_U16 VOPC +V_CMP_GT_U32 VOPC +V_CMP_GT_U64 VOPC +V_CMP_LE_F16 VOPC +V_CMP_LE_F32 VOPC +V_CMP_LE_F64 VOPC +V_CMP_LE_I16 VOPC +V_CMP_LE_I32 VOPC +V_CMP_LE_I64 VOPC +V_CMP_LE_U16 VOPC +V_CMP_LE_U32 VOPC +V_CMP_LE_U64 VOPC +V_CMP_LG_F16 VOPC +V_CMP_LG_F32 VOPC +V_CMP_LG_F64 VOPC +V_CMP_LT_F16 VOPC +V_CMP_LT_F32 VOPC +V_CMP_LT_F64 VOPC +V_CMP_LT_I16 VOPC +V_CMP_LT_I32 VOPC +V_CMP_LT_I64 VOPC +V_CMP_LT_U16 VOPC +V_CMP_LT_U32 VOPC +V_CMP_LT_U64 VOPC +V_CMP_NEQ_F16 VOPC +V_CMP_NEQ_F32 VOPC +V_CMP_NEQ_F64 VOPC +V_CMP_NE_I16 VOPC +V_CMP_NE_I32 VOPC +V_CMP_NE_I64 VOPC +V_CMP_NE_U16 VOPC +V_CMP_NE_U32 VOPC +V_CMP_NE_U64 VOPC +V_CMP_NGE_F16 VOPC +V_CMP_NGE_F32 VOPC +V_CMP_NGE_F64 VOPC +V_CMP_NGT_F16 VOPC +V_CMP_NGT_F32 VOPC +V_CMP_NGT_F64 VOPC +V_CMP_NLE_F16 VOPC +V_CMP_NLE_F32 VOPC +V_CMP_NLE_F64 VOPC +V_CMP_NLG_F16 VOPC +V_CMP_NLG_F32 VOPC +V_CMP_NLG_F64 VOPC +V_CMP_NLT_F16 VOPC +V_CMP_NLT_F32 VOPC +V_CMP_NLT_F64 VOPC +V_CMP_O_F16 VOPC +V_CMP_O_F32 VOPC +V_CMP_O_F64 VOPC +V_CMP_TRU_F16 VOPC +V_CMP_TRU_F32 VOPC +V_CMP_TRU_F64 VOPC +V_CMP_T_I32 VOPC +V_CMP_T_I64 VOPC +V_CMP_T_U32 VOPC +V_CMP_T_U64 VOPC +V_CMP_U_F16 VOPC +V_CMP_U_F32 VOPC +V_CMP_U_F64 VOPC +V_CNDMASK_B32 VOP2 +V_COS_F16 VOP1 +V_COS_F32 VOP1 +V_CUBEID_F32 VOP3 +V_CUBEMA_F32 VOP3 +V_CUBESC_F32 VOP3 +V_CUBETC_F32 VOP3 +V_CVT_F16_F32 VOP1 +V_CVT_F16_I16 VOP1 +V_CVT_F16_U16 VOP1 +V_CVT_F32_F16 VOP1 +V_CVT_F32_F64 VOP1 +V_CVT_F32_I32 VOP1 +V_CVT_F32_U32 VOP1 +V_CVT_F32_UBYTE0 VOP1 +V_CVT_F32_UBYTE1 VOP1 +V_CVT_F32_UBYTE2 VOP1 +V_CVT_F32_UBYTE3 VOP1 +V_CVT_F64_F32 VOP1 +V_CVT_F64_I32 VOP1 +V_CVT_F64_U32 VOP1 +V_CVT_FLR_I32_F32 VOP1 +V_CVT_I16_F16 VOP1 +V_CVT_I32_F32 VOP1 +V_CVT_I32_F64 VOP1 +V_CVT_NORM_I16_F16 VOP1 +V_CVT_NORM_U16_F16 VOP1 +V_CVT_OFF_F32_I4 VOP1 +V_CVT_PKNORM_I16_F16 VOP3 +V_CVT_PKNORM_I16_F32 VOP3 +V_CVT_PKNORM_U16_F16 VOP3 +V_CVT_PKNORM_U16_F32 VOP3 +V_CVT_PKRTZ_F16_F32 VOP2 +V_CVT_PK_I16_I32 VOP3 +V_CVT_PK_U16_U32 VOP3 +V_CVT_PK_U8_F32 VOP3 +V_CVT_RPI_I32_F32 VOP1 +V_CVT_U16_F16 VOP1 +V_CVT_U32_F32 VOP1 +V_CVT_U32_F64 VOP1 +V_DIV_FIXUP_F16 VOP3 +V_DIV_FIXUP_F32 VOP3 +V_DIV_FIXUP_F64 VOP3 +V_DIV_FMAS_F32 VOP3 +V_DIV_FMAS_F64 VOP3 +V_DIV_SCALE_F32 VOP3 +V_DIV_SCALE_F64 VOP3 +V_DOT2C_F32_F16 VOP2 +V_DOT2_F32_F16 VOP3P +V_DOT2_I32_I16 VOP3P +V_DOT2_U32_U16 VOP3P +V_DOT4C_I32_I8 VOP2 +V_DOT4_I32_I8 VOP3P +V_DOT4_U32_U8 VOP3P +V_DOT8_I32_I4 VOP3P +V_DOT8_U32_U4 VOP3P +V_EXP_F16 VOP1 +V_EXP_F32 VOP1 +V_FFBH_I32 VOP1 +V_FFBH_U32 VOP1 +V_FFBL_B32 VOP1 +V_FLOOR_F16 VOP1 +V_FLOOR_F32 VOP1 +V_FLOOR_F64 VOP1 +V_FMAAK_F16 VOP2 +V_FMAAK_F32 VOP2 +V_FMAC_F16 VOP2 +V_FMAC_F32 VOP2 +V_FMAC_LEGACY_F32 VOP2 +V_FMAMK_F16 VOP2 +V_FMAMK_F32 VOP2 +V_FMA_F16 VOP3 +V_FMA_F32 VOP3 +V_FMA_F64 VOP3 +V_FMA_LEGACY_F32 VOP3 +V_FMA_MIXHI_F16 VOP3P +V_FMA_MIXLO_F16 VOP3P +V_FMA_MIX_F32 VOP3P +V_FRACT_F16 VOP1 +V_FRACT_F32 VOP1 +V_FRACT_F64 VOP1 +V_FREXP_EXP_I16_F16 VOP1 +V_FREXP_EXP_I32_F32 VOP1 +V_FREXP_EXP_I32_F64 VOP1 +V_FREXP_MANT_F16 VOP1 +V_FREXP_MANT_F32 VOP1 +V_FREXP_MANT_F64 VOP1 +V_INTERP_MOV_F32 VINTRP +V_INTERP_P1LL_F16 VOP3 +V_INTERP_P1LV_F16 VOP3 +V_INTERP_P1_F32 VINTRP +V_INTERP_P2_F16 VOP3 +V_INTERP_P2_F32 VINTRP +V_LDEXP_F16 VOP2 +V_LDEXP_F32 VOP3 +V_LDEXP_F64 VOP3 +V_LERP_U8 VOP3 +V_LOG_F16 VOP1 +V_LOG_F32 VOP1 +V_LSHLREV_B16 VOP3 +V_LSHLREV_B32 VOP2 +V_LSHLREV_B64 VOP3 +V_LSHL_ADD_U32 VOP3 +V_LSHL_OR_B32 VOP3 +V_LSHRREV_B16 VOP3 +V_LSHRREV_B32 VOP2 +V_LSHRREV_B64 VOP3 +V_MAC_F32 VOP2 +V_MAC_LEGACY_F32 VOP2 +V_MADAK_F32 VOP2 +V_MADMK_F32 VOP2 +V_MAD_F32 VOP3 +V_MAD_I16 VOP3 +V_MAD_I32_I16 VOP3 +V_MAD_I32_I24 VOP3 +V_MAD_I64_I32 VOP3 +V_MAD_LEGACY_F32 VOP3 +V_MAD_U16 VOP3 +V_MAD_U32_U16 VOP3 +V_MAD_U32_U24 VOP3 +V_MAD_U64_U32 VOP3 +V_MAX3_F16 VOP3 +V_MAX3_F32 VOP3 +V_MAX3_I16 VOP3 +V_MAX3_I32 VOP3 +V_MAX3_U16 VOP3 +V_MAX3_U32 VOP3 +V_MAX_F16 VOP2 +V_MAX_F32 VOP2 +V_MAX_F64 VOP3 +V_MAX_I16 VOP3 +V_MAX_I32 VOP2 +V_MAX_U16 VOP3 +V_MAX_U32 VOP2 +V_MBCNT_HI_U32_B32 VOP3 +V_MBCNT_LO_U32_B32 VOP3 +V_MED3_F16 VOP3 +V_MED3_F32 VOP3 +V_MED3_I16 VOP3 +V_MED3_I32 VOP3 +V_MED3_U16 VOP3 +V_MED3_U32 VOP3 +V_MIN3_F16 VOP3 +V_MIN3_F32 VOP3 +V_MIN3_I16 VOP3 +V_MIN3_I32 VOP3 +V_MIN3_U16 VOP3 +V_MIN3_U32 VOP3 +V_MIN_F16 VOP2 +V_MIN_F32 VOP2 +V_MIN_F64 VOP3 +V_MIN_I16 VOP3 +V_MIN_I32 VOP2 +V_MIN_U16 VOP3 +V_MIN_U32 VOP2 +V_MOVRELD_B32 VOP1 +V_MOVRELSD_2_B32 VOP1 +V_MOVRELSD_B32 VOP1 +V_MOVRELS_B32 VOP1 +V_MOV_B32 VOP1 +V_MQSAD_PK_U16_U8 VOP3 +V_MQSAD_U32_U8 VOP3 +V_MSAD_U8 VOP3 +V_MULLIT_F32 VOP3 +V_MUL_F16 VOP2 +V_MUL_F32 VOP2 +V_MUL_F64 VOP3 +V_MUL_HI_I32 VOP3 +V_MUL_HI_I32_I24 VOP2 +V_MUL_HI_U32 VOP3 +V_MUL_HI_U32_U24 VOP2 +V_MUL_I32_I24 VOP2 +V_MUL_LEGACY_F32 VOP2 +V_MUL_LO_U16 VOP3 +V_MUL_LO_U32 VOP3 +V_MUL_U32_U24 VOP2 +V_NOP VOP1 +V_NOT_B32 VOP1 +V_OR3_B32 VOP3 +V_OR_B32 VOP2 +V_PACK_B32_F16 VOP3 +V_PERMLANE16_B32 VOP3 +V_PERMLANEX16_B32 VOP3 +V_PERM_B32 VOP3 +V_PIPEFLUSH VOP1 +V_PK_ADD_F16 VOP3P +V_PK_ADD_I16 VOP3P +V_PK_ADD_U16 VOP3P +V_PK_ASHRREV_I16 VOP3P +V_PK_FMAC_F16 VOP2 +V_PK_FMA_F16 VOP3P +V_PK_LSHLREV_B16 VOP3P +V_PK_LSHRREV_B16 VOP3P +V_PK_MAD_I16 VOP3P +V_PK_MAD_U16 VOP3P +V_PK_MAX_F16 VOP3P +V_PK_MAX_I16 VOP3P +V_PK_MAX_U16 VOP3P +V_PK_MIN_F16 VOP3P +V_PK_MIN_I16 VOP3P +V_PK_MIN_U16 VOP3P +V_PK_MUL_F16 VOP3P +V_PK_MUL_LO_U16 VOP3P +V_PK_SUB_I16 VOP3P +V_PK_SUB_U16 VOP3P +V_QSAD_PK_U16_U8 VOP3 +V_RCP_F16 VOP1 +V_RCP_F32 VOP1 +V_RCP_F64 VOP1 +V_RCP_IFLAG_F32 VOP1 +V_READFIRSTLANE_B32 VOP1 +V_READLANE_B32 VOP3 +V_RNDNE_F16 VOP1 +V_RNDNE_F32 VOP1 +V_RNDNE_F64 VOP1 +V_RSQ_F16 VOP1 +V_RSQ_F32 VOP1 +V_RSQ_F64 VOP1 +V_SAD_HI_U8 VOP3 +V_SAD_U16 VOP3 +V_SAD_U32 VOP3 +V_SAD_U8 VOP3 +V_SAT_PK_U8_I16 VOP1 +V_SIN_F16 VOP1 +V_SIN_F32 VOP1 +V_SQRT_F16 VOP1 +V_SQRT_F32 VOP1 +V_SQRT_F64 VOP1 +V_SUBREV_CO_CI_U32 VOP2 +V_SUBREV_CO_U32 VOP3 +V_SUBREV_F16 VOP2 +V_SUBREV_F32 VOP2 +V_SUBREV_NC_U32 VOP2 +V_SUB_CO_CI_U32 VOP2 +V_SUB_CO_U32 VOP3 +V_SUB_F16 VOP2 +V_SUB_F32 VOP2 +V_SUB_NC_I16 VOP3 +V_SUB_NC_I32 VOP3 +V_SUB_NC_U16 VOP3 +V_SUB_NC_U32 VOP2 +V_SWAPREL_B32 VOP1 +V_SWAP_B32 VOP1 +V_TRIG_PREOP_F64 VOP3 +V_TRUNC_F16 VOP1 +V_TRUNC_F32 VOP1 +V_TRUNC_F64 VOP1 +V_WRITELANE_B32 VOP3 +V_XAD_U32 VOP3 +V_XNOR_B32 VOP2 +V_XOR3_B32 VOP3 +V_XOR_B32 VOP2