feat(shader): implement the D16 byte/short loads and high-half stores
buffer/flat/global/scratch_load_{ubyte,sbyte,short}_d16(_hi),
buffer/flat/global/scratch_store_{byte,short}_d16_hi and
ds_read_{u8,i8}_d16(_hi), ds_write_b8_d16_hi threw in the decoder. They use
the same 16-bit destination/source select as the existing ds_read_u16_d16
and ds_write_b16_d16_hi: a load writes one half and keeps the other, a
_d16_hi store takes its data from the high half.
Co-Authored-By: Claude <noreply@anthropic.com>
This commit is contained in:
Adrià Franch
parent
d3ec1f15fb
commit
504a2fd8af
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@ -0,0 +1,118 @@
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#include "prx/libSceAgcDriver/Execution/include/VulkanDevice.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/Draw.hpp"
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#include "Recompiler.hpp"
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#include "VulkanTestDevice.hpp"
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#include <algorithm>
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#include <array>
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#include <cstdint>
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#include <cstdio>
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#include <cstring>
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#include <iostream>
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#include <string>
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#include <vector>
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namespace {
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using AgcDriver::Graphics::Require;
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using ShaderRecompiler::ShaderStage;
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constexpr std::uint32_t Threads = 32;
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constexpr std::uint32_t InputBytes = 16;
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constexpr std::uint32_t Results = 16;
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alignas(256) std::array<std::uint8_t, Threads * InputBytes> Input{};
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alignas(256) std::array<std::uint32_t, Threads * Results> Output{};
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alignas(256) constexpr std::array<std::uint32_t, 107> D16Code{
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0x34020084, 0x34060086, 0xbe880300, 0x8709ff01, 0x0000ffff, 0x7e1402ff, 0xabcdabcd, 0x7e1602ff,
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0xabcdabcd, 0x7e1802ff, 0xabcdabcd, 0x7e1a02ff, 0xabcdabcd, 0x7e1c02ff, 0xabcdabcd, 0x7e1e02ff,
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0xabcdabcd, 0x7e2002ff, 0xabcdabcd, 0x7e2202ff, 0xabcdabcd, 0x7e2402ff, 0xabcdabcd, 0x7e2602ff,
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0xabcdabcd, 0x7e2802ff, 0xabcdabcd, 0x7e2a02ff, 0xabcdabcd, 0xe0801001, 0x80000a01, 0xe0841002,
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0x80000a01, 0xe0881003, 0x80000b01, 0xe08c1005, 0x80000b01, 0xe0901006, 0x80000c01, 0xe0941008,
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0x80000c01, 0xdc808001, 0x0d080001, 0xdc848002, 0x0d080001, 0xdc888003, 0x0e080001, 0xdc8c8005,
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0x0e080001, 0xdc908006, 0x0f080001, 0xdc948008, 0x0f080001, 0x34040082, 0xbf8c3f70, 0xe0301000,
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0x80000401, 0xbf8c3f70, 0xd8340000, 0x00000402, 0xbf8cc07f, 0xda880001, 0x10000002, 0xda8c0002,
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0x10000002, 0xda900003, 0x11000002, 0xda940001, 0x11000002, 0xda980002, 0x12000002, 0xda9c0000,
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0x12000002, 0xbf8cc07f, 0x7e2602ff, 0x80c1a2b3, 0xe0641028, 0x80011303, 0xe06c102c, 0x80011303,
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0xda800001, 0x00001302, 0xbf8cc07f, 0xd8d80000, 0x14000002, 0xbf8c0070, 0xe0701000, 0x80010a03,
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0xe0701004, 0x80010b03, 0xe0701008, 0x80010c03, 0xe070100c, 0x80010d03, 0xe0701010, 0x80010e03,
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0xe0701014, 0x80010f03, 0xe0701018, 0x80011003, 0xe070101c, 0x80011103, 0xe0701020, 0x80011203,
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0xe0701024, 0x80011403, 0xbf810000,
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};
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std::array<std::uint32_t, 4> BufferDescriptor(const void* data, std::uint32_t bytes) {
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const auto address = reinterpret_cast<std::uintptr_t>(data);
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return {static_cast<std::uint32_t>(address), static_cast<std::uint32_t>((address >> 32u) & 0xffffu), bytes, 0x01016facu};
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}
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void Run(AgcDriver::VulkanDevice& device) {
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for (std::uint32_t i = 0; i < Input.size(); ++i) Input[i] = static_cast<std::uint8_t>(i * 37u + 0x81u);
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Output.fill(0xdeadbeefu);
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std::vector<std::uint32_t> userData(8, 0u);
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const auto input = BufferDescriptor(Input.data(), static_cast<std::uint32_t>(Input.size()));
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const auto output = BufferDescriptor(Output.data(), static_cast<std::uint32_t>(Output.size() * 4u));
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std::copy(input.begin(), input.end(), userData.begin());
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std::copy(output.begin(), output.end(), userData.begin() + 4);
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const std::span<const std::uint32_t> code(D16Code);
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const std::array<ShaderRecompiler::MemoryRegion, 1> memory{{{reinterpret_cast<std::uintptr_t>(code.data()), std::as_bytes(code)}}};
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const ShaderRecompiler::ShaderComputeStageInfo compute{{Threads, 1, 1}, 4u * Threads, {false, false, false}, false, 1};
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ShaderRecompiler::RecompileRequest request{
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{ShaderStage::Compute, reinterpret_cast<std::uintptr_t>(code.data()), code, 0, {}},
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{32, 0, userData, compute, std::nullopt, std::nullopt, memory},
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device.Target(),
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{0, 0, 0, 128}
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};
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request.useCache = false;
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const auto result = ShaderRecompiler::Recompile(request);
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device.Dispatch(result, 1, 1, 1, {}, reinterpret_cast<std::uintptr_t>(code.data()));
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device.WaitIdle();
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}
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std::string Hex(std::uint32_t value) {
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char text[16];
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std::snprintf(text, sizeof(text), "0x%08x", value);
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return text;
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}
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void Check() {
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constexpr std::array<const char*, 12> names{
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"buffer_load_ubyte_d16(_hi)", "buffer_load_sbyte_d16(_hi)", "buffer_load_short_d16(_hi)",
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"global_load_ubyte_d16(_hi)", "global_load_sbyte_d16(_hi)", "global_load_short_d16(_hi)",
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"ds_read_u8_d16(_hi)", "ds_read_i8_d16(_hi)", "ds_read_u16_d16(_hi)", "ds_write_b8_d16_hi",
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"buffer_store_byte_d16_hi", "buffer_store_short_d16_hi",
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};
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for (std::uint32_t tid = 0; tid < Threads; ++tid) {
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const std::uint8_t* in = &Input[tid * InputBytes];
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const auto u8 = [&](std::uint32_t at) { return static_cast<std::uint32_t>(in[at]); };
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const auto i8 = [&](std::uint32_t at) { return static_cast<std::uint32_t>(static_cast<std::int16_t>(static_cast<std::int8_t>(in[at]))) & 0xffffu; };
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const auto u16 = [&](std::uint32_t at) { return u8(at) | (u8(at + 1u) << 8u); };
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const std::uint32_t loads[3] = {u8(1) | (u8(2) << 16u), i8(3) | (i8(5) << 16u), u16(6) | (u16(8) << 16u)};
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std::uint32_t dword = 0;
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std::memcpy(&dword, in, 4);
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const std::uint32_t written = (dword & 0xffff00ffu) | (0xc1u << 8u);
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std::array<std::uint32_t, 12> expected{
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loads[0], loads[1], loads[2], loads[0], loads[1], loads[2],
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u8(1) | (u8(2) << 16u), i8(3) | (i8(1) << 16u), u16(2) | (u16(0) << 16u), written,
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0xdeadbec1u, 0xdead80c1u,
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};
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const auto* out = &Output[tid * Results];
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for (std::uint32_t j = 0; j < expected.size(); ++j) {
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Require(out[j] == expected[j], std::string("d16 memory: lane ") + std::to_string(tid) + " " + names[j] + " is " + Hex(out[j]) + ", expected " + Hex(expected[j]));
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}
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}
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}
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}
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int main() {
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try {
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const auto device = OpenVulkanTestDevice();
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if (!device) return VulkanTestSkipped;
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Run(*device);
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Check();
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std::puts("d16 memory tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@ -638,6 +638,14 @@ enum class RdnaOpcode : std::uint16_t {
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BufferLoadDwordx3,
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BufferStoreByte,
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BufferStoreShort,
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BufferLoadUbyteD16,
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BufferLoadUbyteD16Hi,
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BufferLoadSbyteD16,
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BufferLoadSbyteD16Hi,
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BufferLoadShortD16,
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BufferLoadShortD16Hi,
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BufferStoreByteD16Hi,
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BufferStoreShortD16Hi,
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BufferStoreDwordx2,
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BufferStoreDwordx3,
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TbufferLoadFormatX,
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@ -673,6 +681,14 @@ enum class RdnaOpcode : std::uint16_t {
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FlatLoadDwordx4,
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FlatStoreByte,
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FlatStoreShort,
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FlatLoadUbyteD16,
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FlatLoadUbyteD16Hi,
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FlatLoadSbyteD16,
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FlatLoadSbyteD16Hi,
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FlatLoadShortD16,
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FlatLoadShortD16Hi,
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FlatStoreByteD16Hi,
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FlatStoreShortD16Hi,
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FlatStoreDword,
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FlatStoreDwordx2,
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FlatStoreDwordx3,
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@ -736,6 +752,11 @@ enum class RdnaOpcode : std::uint16_t {
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DsCmpstRtnF32,
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DsWrapRtnB32,
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DsNop,
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DsReadU8D16,
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DsReadU8D16Hi,
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DsReadI8D16,
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DsReadI8D16Hi,
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DsWriteB8D16Hi,
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DsWrite2st64B32,
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DsWrite2B64,
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DsWrite2st64B64,
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@ -8,6 +8,37 @@ namespace ShaderRecompiler {
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namespace {
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RdnaOperand d16Half(RdnaOperand operand, RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::BufferLoadUbyteD16:
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case RdnaOpcode::BufferLoadSbyteD16:
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case RdnaOpcode::BufferLoadShortD16:
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case RdnaOpcode::FlatLoadUbyteD16:
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case RdnaOpcode::FlatLoadSbyteD16:
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case RdnaOpcode::FlatLoadShortD16:
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case RdnaOpcode::DsReadU8D16:
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case RdnaOpcode::DsReadI8D16:
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case RdnaOpcode::DsReadU16D16: operand.sdwaSel = 4u; break;
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case RdnaOpcode::BufferLoadUbyteD16Hi:
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case RdnaOpcode::BufferLoadSbyteD16Hi:
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case RdnaOpcode::BufferLoadShortD16Hi:
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case RdnaOpcode::BufferStoreByteD16Hi:
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case RdnaOpcode::BufferStoreShortD16Hi:
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case RdnaOpcode::FlatLoadUbyteD16Hi:
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case RdnaOpcode::FlatLoadSbyteD16Hi:
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case RdnaOpcode::FlatLoadShortD16Hi:
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case RdnaOpcode::FlatStoreByteD16Hi:
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case RdnaOpcode::FlatStoreShortD16Hi:
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case RdnaOpcode::DsReadU8D16Hi:
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case RdnaOpcode::DsReadI8D16Hi:
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case RdnaOpcode::DsReadU16D16Hi:
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case RdnaOpcode::DsWriteB8D16Hi:
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case RdnaOpcode::DsWriteB16D16Hi: operand.sdwaSel = 5u; break;
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default: break;
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}
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return operand;
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}
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struct MemoryOpcodeInfo {
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std::uint32_t encoding;
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RdnaOpcode opcode;
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@ -54,6 +85,14 @@ constexpr MemoryOpcodeInfo mubufOpcodes[] = {
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{0x1du, RdnaOpcode::BufferStoreDwordx2, 2, 32, false, false, false},
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{0x1eu, RdnaOpcode::BufferStoreDwordx4, 4, 32, false, false, false},
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{0x1fu, RdnaOpcode::BufferStoreDwordx3, 3, 32, false, false, false},
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{0x20u, RdnaOpcode::BufferLoadUbyteD16, 1, 8, false, false, false},
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{0x21u, RdnaOpcode::BufferLoadUbyteD16Hi, 1, 8, false, false, false},
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{0x22u, RdnaOpcode::BufferLoadSbyteD16, 1, 8, true, false, false},
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{0x23u, RdnaOpcode::BufferLoadSbyteD16Hi, 1, 8, true, false, false},
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{0x24u, RdnaOpcode::BufferLoadShortD16, 1, 16, false, false, false},
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{0x25u, RdnaOpcode::BufferLoadShortD16Hi, 1, 16, false, false, false},
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{0x19u, RdnaOpcode::BufferStoreByteD16Hi, 1, 8, false, false, false},
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{0x1bu, RdnaOpcode::BufferStoreShortD16Hi, 1, 16, false, false, false},
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{0x30u, RdnaOpcode::BufferAtomicSwap, 1, 32, false, false, false},
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{0x31u, RdnaOpcode::BufferAtomicCmpswap, 1, 32, false, false, false},
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{0x32u, RdnaOpcode::BufferAtomicAdd, 1, 32, false, false, false},
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@ -97,6 +136,14 @@ constexpr MemoryOpcodeInfo flatOpcodes[] = {
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{0x1du, RdnaOpcode::FlatStoreDwordx2, 2, 32, false, false, false},
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{0x1eu, RdnaOpcode::FlatStoreDwordx4, 4, 32, false, false, false},
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{0x1fu, RdnaOpcode::FlatStoreDwordx3, 3, 32, false, false, false},
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{0x20u, RdnaOpcode::FlatLoadUbyteD16, 1, 8, false, false, false},
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{0x21u, RdnaOpcode::FlatLoadUbyteD16Hi, 1, 8, false, false, false},
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{0x22u, RdnaOpcode::FlatLoadSbyteD16, 1, 8, true, false, false},
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{0x23u, RdnaOpcode::FlatLoadSbyteD16Hi, 1, 8, true, false, false},
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{0x24u, RdnaOpcode::FlatLoadShortD16, 1, 16, false, false, false},
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{0x25u, RdnaOpcode::FlatLoadShortD16Hi, 1, 16, false, false, false},
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{0x19u, RdnaOpcode::FlatStoreByteD16Hi, 1, 8, false, false, false},
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{0x1bu, RdnaOpcode::FlatStoreShortD16Hi, 1, 16, false, false, false},
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};
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constexpr MemoryOpcodeInfo dsOpcodes[] = {
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@ -160,7 +207,12 @@ constexpr MemoryOpcodeInfo dsOpcodes[] = {
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{0x76u, RdnaOpcode::DsReadB64, 2, 32, false, false, false},
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{0x77u, RdnaOpcode::DsRead2B64, 4, 32, false, false, false},
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{0x78u, RdnaOpcode::DsRead2st64B64, 4, 32, false, false, false},
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{0xa0u, RdnaOpcode::DsWriteB8D16Hi, 1, 8, false, false, false},
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{0xa1u, RdnaOpcode::DsWriteB16D16Hi, 1, 16, false, false, false},
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{0xa2u, RdnaOpcode::DsReadU8D16, 1, 8, false, false, false},
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{0xa3u, RdnaOpcode::DsReadU8D16Hi, 1, 8, false, false, false},
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{0xa4u, RdnaOpcode::DsReadI8D16, 1, 8, true, false, false},
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{0xa5u, RdnaOpcode::DsReadI8D16Hi, 1, 8, true, false, false},
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{0xa6u, RdnaOpcode::DsReadU16D16, 1, 16, false, false, false},
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{0xa7u, RdnaOpcode::DsReadU16D16Hi, 1, 16, false, false, false},
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{0xb0u, RdnaOpcode::DsWriteAddtidB32, 1, 32, false, false, false},
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@ -282,6 +334,7 @@ bool isDsWriteOpcode(RdnaOpcode opcode) {
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case RdnaOpcode::DsWriteB8:
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case RdnaOpcode::DsWriteB16:
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case RdnaOpcode::DsWriteB16D16Hi:
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case RdnaOpcode::DsWriteB8D16Hi:
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case RdnaOpcode::DsWrite2B32:
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case RdnaOpcode::DsWrite2st64B32:
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case RdnaOpcode::DsWrite2B64:
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@ -358,6 +411,8 @@ bool isFlatStoreOpcode(RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::FlatStoreByte:
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case RdnaOpcode::FlatStoreShort:
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case RdnaOpcode::FlatStoreByteD16Hi:
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case RdnaOpcode::FlatStoreShortD16Hi:
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case RdnaOpcode::FlatStoreDword:
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case RdnaOpcode::FlatStoreDwordx2:
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case RdnaOpcode::FlatStoreDwordx3:
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@ -503,7 +558,7 @@ RdnaInstruction DecodeRdnaMubuf(std::uint32_t programCounter, std::span<const st
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applyMemoryInfo(instruction, info);
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setRawWords(instruction, code, wordIndex, 2u);
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instruction.destination = vectorRegister(vdata);
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instruction.destination = d16Half(vectorRegister(vdata), instruction.op);
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instruction.source0 = vectorRegister(vaddr);
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instruction.source1 = scalarDescriptorBase(srsrc * 4u, 4u, "MUBUF resource descriptor register range overflow");
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instruction.source2 = scalarSource(soffsetCode);
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@ -586,7 +641,7 @@ RdnaInstruction DecodeRdnaFlat(std::uint32_t programCounter, std::span<const std
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applyMemoryInfo(instruction, info);
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setRawWords(instruction, code, wordIndex, 2u);
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instruction.destination = vectorRegister(isFlatStoreOpcode(instruction.op) ? data : vdst);
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instruction.destination = d16Half(vectorRegister(isFlatStoreOpcode(instruction.op) ? data : vdst), instruction.op);
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instruction.source0 = vectorRegister(addr);
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if (seg == 0u || saddr == 0x7Du || saddr == 0x7Fu) {
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if (addr == 255u) {
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@ -654,17 +709,9 @@ RdnaInstruction DecodeRdnaDs(std::uint32_t programCounter, std::span<const std::
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instruction.secondaryOffset = offset1 * 512u;
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}
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instruction.destination = vectorRegister(vdst);
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if (instruction.op == RdnaOpcode::DsReadU16D16) {
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instruction.destination.sdwaSel = 4u;
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} else if (instruction.op == RdnaOpcode::DsReadU16D16Hi) {
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instruction.destination.sdwaSel = 5u;
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}
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instruction.destination = d16Half(vectorRegister(vdst), instruction.op);
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instruction.source0 = vectorRegister(addr);
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instruction.source1 = vectorRegister(data0);
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if (instruction.op == RdnaOpcode::DsWriteB16D16Hi) {
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instruction.source1.sdwaSel = 5u;
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}
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instruction.source1 = isDsWriteOpcode(instruction.op) ? d16Half(vectorRegister(data0), instruction.op) : vectorRegister(data0);
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instruction.source2 = vectorRegister(data1);
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instruction.sourceCount = dsSourceCount(instruction.op);
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return instruction;
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@ -631,6 +631,14 @@ bool IsBufferMemoryOpcode(RdnaOpcode opcode) {
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case RdnaOpcode::BufferLoadDwordx3:
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case RdnaOpcode::BufferStoreByte:
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case RdnaOpcode::BufferStoreShort:
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case RdnaOpcode::BufferLoadUbyteD16:
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case RdnaOpcode::BufferLoadUbyteD16Hi:
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case RdnaOpcode::BufferLoadSbyteD16:
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case RdnaOpcode::BufferLoadSbyteD16Hi:
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case RdnaOpcode::BufferLoadShortD16:
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case RdnaOpcode::BufferLoadShortD16Hi:
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case RdnaOpcode::BufferStoreByteD16Hi:
|
||||
case RdnaOpcode::BufferStoreShortD16Hi:
|
||||
case RdnaOpcode::BufferStoreDwordx2:
|
||||
case RdnaOpcode::BufferStoreDwordx3:
|
||||
case RdnaOpcode::BufferAtomicSwap:
|
||||
|
|
|
|||
|
|
@ -53,6 +53,12 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
case RdnaOpcode::BufferLoadSbyte:
|
||||
case RdnaOpcode::BufferLoadUshort:
|
||||
case RdnaOpcode::BufferLoadSshort:
|
||||
case RdnaOpcode::BufferLoadUbyteD16:
|
||||
case RdnaOpcode::BufferLoadUbyteD16Hi:
|
||||
case RdnaOpcode::BufferLoadSbyteD16:
|
||||
case RdnaOpcode::BufferLoadSbyteD16Hi:
|
||||
case RdnaOpcode::BufferLoadShortD16:
|
||||
case RdnaOpcode::BufferLoadShortD16Hi:
|
||||
case RdnaOpcode::BufferLoadDword:
|
||||
case RdnaOpcode::BufferLoadDwordx2:
|
||||
case RdnaOpcode::BufferLoadDwordx3:
|
||||
|
|
@ -69,6 +75,8 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
case RdnaOpcode::BufferStoreFormatXyzw:
|
||||
case RdnaOpcode::BufferStoreByte:
|
||||
case RdnaOpcode::BufferStoreShort:
|
||||
case RdnaOpcode::BufferStoreByteD16Hi:
|
||||
case RdnaOpcode::BufferStoreShortD16Hi:
|
||||
case RdnaOpcode::BufferStoreDword:
|
||||
case RdnaOpcode::BufferStoreDwordx2:
|
||||
case RdnaOpcode::BufferStoreDwordx3:
|
||||
|
|
@ -114,6 +122,12 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
case RdnaOpcode::FlatLoadSbyte:
|
||||
case RdnaOpcode::FlatLoadUshort:
|
||||
case RdnaOpcode::FlatLoadSshort:
|
||||
case RdnaOpcode::FlatLoadUbyteD16:
|
||||
case RdnaOpcode::FlatLoadUbyteD16Hi:
|
||||
case RdnaOpcode::FlatLoadSbyteD16:
|
||||
case RdnaOpcode::FlatLoadSbyteD16Hi:
|
||||
case RdnaOpcode::FlatLoadShortD16:
|
||||
case RdnaOpcode::FlatLoadShortD16Hi:
|
||||
case RdnaOpcode::FlatLoadDword:
|
||||
case RdnaOpcode::FlatLoadDwordx2:
|
||||
case RdnaOpcode::FlatLoadDwordx3:
|
||||
|
|
@ -121,6 +135,8 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
return flatLoad(inst);
|
||||
case RdnaOpcode::FlatStoreByte:
|
||||
case RdnaOpcode::FlatStoreShort:
|
||||
case RdnaOpcode::FlatStoreByteD16Hi:
|
||||
case RdnaOpcode::FlatStoreShortD16Hi:
|
||||
case RdnaOpcode::FlatStoreDword:
|
||||
case RdnaOpcode::FlatStoreDwordx2:
|
||||
case RdnaOpcode::FlatStoreDwordx3:
|
||||
|
|
@ -231,6 +247,10 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
case RdnaOpcode::DsReadU16:
|
||||
case RdnaOpcode::DsReadU16D16:
|
||||
case RdnaOpcode::DsReadU16D16Hi:
|
||||
case RdnaOpcode::DsReadU8D16:
|
||||
case RdnaOpcode::DsReadU8D16Hi:
|
||||
case RdnaOpcode::DsReadI8D16:
|
||||
case RdnaOpcode::DsReadI8D16Hi:
|
||||
case RdnaOpcode::DsReadB32:
|
||||
case RdnaOpcode::DsReadB64:
|
||||
case RdnaOpcode::DsReadB96:
|
||||
|
|
@ -244,6 +264,7 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
case RdnaOpcode::DsWriteB8:
|
||||
case RdnaOpcode::DsWriteB16:
|
||||
case RdnaOpcode::DsWriteB16D16Hi:
|
||||
case RdnaOpcode::DsWriteB8D16Hi:
|
||||
case RdnaOpcode::DsWriteB32:
|
||||
case RdnaOpcode::DsWriteB64:
|
||||
case RdnaOpcode::DsWriteB96:
|
||||
|
|
|
|||
Loading…
Reference in New Issue