feat(shader): implement the 32-bit DS src2 operations
The decoder threw on the GFX10.1 DS src2 opcodes 0x80-0x8b, 0x8d, 0x92, 0x93 and 0x95. Each reads DS[B], where B is the address plus four times the 15-bit signed offset in offset1[6:0]:offset0, and applies the matching operation to DS[A]: add, sub, rsub, inc, dec, signed and unsigned min and max, and, or, xor, f32 min, max and add through the 32-bit LDS atomics, and a plain write for ds_write_src2_b32. The form that takes the offset from the address bits (offset1[7]), the 64-bit forms and GDS still throw. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
Claude
Adrià Franch
parent
0447793216
commit
c0519cc814
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@ -0,0 +1,152 @@
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#include "prx/libSceAgcDriver/Execution/include/VulkanDevice.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/Draw.hpp"
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#include "Recompiler.hpp"
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#include "VulkanTestDevice.hpp"
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#include <algorithm>
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#include <array>
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#include <bit>
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#include <cstdint>
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#include <cstdio>
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#include <iostream>
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#include <string>
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#include <vector>
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namespace {
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using AgcDriver::Graphics::Require;
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using ShaderRecompiler::ShaderStage;
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constexpr std::uint32_t Threads = 32;
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constexpr std::uint32_t Inputs = 4;
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constexpr std::uint32_t Results = 16;
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alignas(256) std::array<std::uint32_t, Threads * Inputs> Input{};
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alignas(256) std::array<std::uint32_t, Threads * Results> Output{};
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alignas(256) constexpr std::array<std::uint32_t, 207> Code{
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0x34020084, 0xe0381000, 0x80000201, 0x340c0082, 0xbf8c3f70, 0x4a0e0cff, 0x00001000, 0x4a100c80,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda007c00, 0x00000007, 0xd8d80000, 0x0a000007,
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0x4a0e0cff, 0x00001080, 0x4a100cff, 0x00002080, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda040400, 0x00000007, 0xd8d80000, 0x0b000007, 0x4a0e0cff, 0x00001100, 0x4a100cff, 0x00000100,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda087c00, 0x00000007, 0xd8d80000, 0x0c000007,
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0x4a0e0cff, 0x00001180, 0x4a100cff, 0x00002180, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda0c0400, 0x00000007, 0xd8d80000, 0x0d000007, 0x4a0e0cff, 0x00001200, 0x4a100cff, 0x00000200,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda107c00, 0x00000007, 0xd8d80000, 0x0e000007,
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0x4a0e0cff, 0x00001280, 0x4a100cff, 0x00002280, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda140400, 0x00000007, 0xd8d80000, 0x0f000007, 0x4a0e0cff, 0x00001300, 0x4a100cff, 0x00000300,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda187c00, 0x00000007, 0xd8d80000, 0x10000007,
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0x4a0e0cff, 0x00001380, 0x4a100cff, 0x00002380, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda1c0400, 0x00000007, 0xd8d80000, 0x11000007, 0x4a0e0cff, 0x00001400, 0x4a100cff, 0x00000400,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda207c00, 0x00000007, 0xd8d80000, 0x12000007,
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0x4a0e0cff, 0x00001480, 0x4a100cff, 0x00002480, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda240400, 0x00000007, 0xd8d80000, 0x13000007, 0x4a0e0cff, 0x00001500, 0x4a100cff, 0x00000500,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda287c00, 0x00000007, 0xd8d80000, 0x14000007,
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0x4a0e0cff, 0x00001580, 0x4a100cff, 0x00002580, 0xd8340000, 0x00000207, 0xd8340000, 0x00000308,
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0xda2c0400, 0x00000007, 0xd8d80000, 0x15000007, 0x4a0e0cff, 0x00001600, 0x4a100cff, 0x00000600,
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0xd8340000, 0x00000207, 0xd8340000, 0x00000308, 0xda347c00, 0x00000007, 0xd8d80000, 0x16000007,
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0x4a0e0cff, 0x00001680, 0x4a100cff, 0x00002680, 0xd8340000, 0x00000407, 0xd8340000, 0x00000508,
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0xda480400, 0x00000007, 0xd8d80000, 0x17000007, 0x4a0e0cff, 0x00001700, 0x4a100cff, 0x00000700,
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0xd8340000, 0x00000407, 0xd8340000, 0x00000508, 0xda4c7c00, 0x00000007, 0xd8d80000, 0x18000007,
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0x4a0e0cff, 0x00001780, 0x4a100cff, 0x00002780, 0xd8340000, 0x00000407, 0xd8340000, 0x00000508,
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0xda540400, 0x00000007, 0xd8d80000, 0x19000007, 0x34020086, 0xbf8cc07f, 0xe0781000, 0x80010a01,
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0xe0781010, 0x80010e01, 0xe0781020, 0x80011201, 0xe0781030, 0x80011601, 0xbf810000,
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};
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alignas(256) constexpr std::array<std::uint32_t, 3> AddressOffsetCode{0xda008000, 0x00000000, 0xbf810000};
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void Fill(std::uint32_t tid, std::uint32_t* words) {
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const std::uint64_t seed = (tid + 1u) * 0x9e3779b97f4a7c15ull;
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const auto mixed = seed * 0xbf58476d1ce4e5b9ull;
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words[0] = tid % 4u == 0u ? tid % 7u : static_cast<std::uint32_t>(seed);
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words[1] = tid % 4u == 0u ? (tid * 3u) % 7u : tid % 4u == 1u ? words[0] : static_cast<std::uint32_t>(mixed >> 32u);
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words[2] = std::bit_cast<std::uint32_t>(static_cast<float>(static_cast<std::int32_t>(tid % 9u) - 4) * 1.75f + 0.5f);
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words[3] = std::bit_cast<std::uint32_t>(static_cast<float>(static_cast<std::int32_t>((tid * 5u) % 11u) - 5) * 0.625f + 0.25f);
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}
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std::array<std::uint32_t, 4> BufferDescriptor(const void* data, std::uint32_t bytes) {
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const auto address = reinterpret_cast<std::uintptr_t>(data);
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return {static_cast<std::uint32_t>(address), static_cast<std::uint32_t>((address >> 32u) & 0xffffu), bytes, 0x01016facu};
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}
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std::string Hex(std::uint32_t value) {
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char text[16];
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std::snprintf(text, sizeof(text), "0x%08x", value);
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return text;
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}
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ShaderRecompiler::RecompileResult Compile(AgcDriver::VulkanDevice& device, std::span<const std::uint32_t> code) {
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std::vector<std::uint32_t> userData(8, 0u);
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const auto input = BufferDescriptor(Input.data(), static_cast<std::uint32_t>(Input.size() * 4u));
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const auto output = BufferDescriptor(Output.data(), static_cast<std::uint32_t>(Output.size() * 4u));
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std::copy(input.begin(), input.end(), userData.begin());
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std::copy(output.begin(), output.end(), userData.begin() + 4);
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const std::array<ShaderRecompiler::MemoryRegion, 1> memory{{{reinterpret_cast<std::uintptr_t>(code.data()), std::as_bytes(code)}}};
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const ShaderRecompiler::ShaderComputeStageInfo compute{{Threads, 1, 1}, 10240u, {false, false, false}, false, 1};
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ShaderRecompiler::RecompileRequest request{
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{ShaderStage::Compute, reinterpret_cast<std::uintptr_t>(code.data()), code, 0, {}},
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{32, 0, userData, compute, std::nullopt, std::nullopt, memory},
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device.Target(),
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{0, 0, 0, 128}
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};
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request.useCache = false;
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return ShaderRecompiler::Recompile(request);
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}
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void Run(AgcDriver::VulkanDevice& device) {
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for (std::uint32_t tid = 0; tid < Threads; ++tid) Fill(tid, &Input[tid * Inputs]);
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Output.fill(0xdeadbeefu);
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const auto result = Compile(device, Code);
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device.Dispatch(result, 1, 1, 1, {}, reinterpret_cast<std::uintptr_t>(Code.data()));
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device.WaitIdle();
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}
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void CheckLanes() {
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constexpr std::array<const char*, Results> names{
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"ds_add_src2_u32", "ds_sub_src2_u32", "ds_rsub_src2_u32", "ds_inc_src2_u32", "ds_dec_src2_u32", "ds_min_src2_i32", "ds_max_src2_i32", "ds_min_src2_u32",
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"ds_max_src2_u32", "ds_and_src2_b32", "ds_or_src2_b32", "ds_xor_src2_b32", "ds_write_src2_b32", "ds_min_src2_f32", "ds_max_src2_f32", "ds_add_src2_f32",
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};
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for (std::uint32_t tid = 0; tid < Threads; ++tid) {
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const std::uint32_t* in = &Input[tid * Inputs];
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const std::uint32_t a = in[0];
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const std::uint32_t b = in[1];
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const auto sa = static_cast<std::int32_t>(a);
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const auto sb = static_cast<std::int32_t>(b);
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const float fa = std::bit_cast<float>(in[2]);
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const float fb = std::bit_cast<float>(in[3]);
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const std::array<std::uint32_t, Results> expected{
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a + b, a - b, b - a, a >= b ? 0u : a + 1u, (a == 0u || a > b) ? b : a - 1u,
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static_cast<std::uint32_t>(std::min(sa, sb)), static_cast<std::uint32_t>(std::max(sa, sb)), std::min(a, b), std::max(a, b),
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a & b, a | b, a ^ b, b,
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std::bit_cast<std::uint32_t>(std::min(fa, fb)), std::bit_cast<std::uint32_t>(std::max(fa, fb)), std::bit_cast<std::uint32_t>(fa + fb),
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};
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for (std::uint32_t op = 0; op < Results; ++op) {
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const std::uint32_t actual = Output[tid * Results + op];
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Require(actual == expected[op], "lds src2: lane " + std::to_string(tid) + " " + names[op] + " is " + Hex(actual) + ", expected " + Hex(expected[op]));
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}
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}
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}
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void CheckAddressOffsetRejected(AgcDriver::VulkanDevice& device) {
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try {
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(void)Compile(device, AddressOffsetCode);
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} catch (const std::exception&) {
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return;
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}
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Require(false, "lds src2: an offset taken from the address was accepted");
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}
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}
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int main() {
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try {
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const auto device = OpenVulkanTestDevice();
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if (!device) return VulkanTestSkipped;
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Run(*device);
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CheckLanes();
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CheckAddressOffsetRejected(*device);
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std::puts("lds src2 tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@ -938,6 +938,22 @@ enum class RdnaOpcode : std::uint16_t {
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DsCmpstRtnF64,
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DsMinRtnF64,
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DsMaxRtnF64,
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DsAddSrc2U32,
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DsSubSrc2U32,
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DsRsubSrc2U32,
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DsIncSrc2U32,
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DsDecSrc2U32,
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DsMinSrc2I32,
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DsMaxSrc2I32,
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DsMinSrc2U32,
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DsMaxSrc2U32,
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DsAndSrc2B32,
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DsOrSrc2B32,
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DsXorSrc2B32,
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DsWriteSrc2B32,
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DsMinSrc2F32,
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DsMaxSrc2F32,
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DsAddSrc2F32,
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DsNop,
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DsReadU8D16,
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DsReadU8D16Hi,
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@ -283,6 +283,22 @@ constexpr MemoryOpcodeInfo dsOpcodes[] = {
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{0x71u, RdnaOpcode::DsCmpstRtnF64, 2, 32, false, false, false},
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{0x72u, RdnaOpcode::DsMinRtnF64, 2, 32, false, false, false},
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{0x73u, RdnaOpcode::DsMaxRtnF64, 2, 32, false, false, false},
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{0x80u, RdnaOpcode::DsAddSrc2U32, 1, 32, false, false, false},
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{0x81u, RdnaOpcode::DsSubSrc2U32, 1, 32, false, false, false},
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{0x82u, RdnaOpcode::DsRsubSrc2U32, 1, 32, false, false, false},
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{0x83u, RdnaOpcode::DsIncSrc2U32, 1, 32, false, false, false},
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{0x84u, RdnaOpcode::DsDecSrc2U32, 1, 32, false, false, false},
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{0x85u, RdnaOpcode::DsMinSrc2I32, 1, 32, false, false, false},
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{0x86u, RdnaOpcode::DsMaxSrc2I32, 1, 32, false, false, false},
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{0x87u, RdnaOpcode::DsMinSrc2U32, 1, 32, false, false, false},
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{0x88u, RdnaOpcode::DsMaxSrc2U32, 1, 32, false, false, false},
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{0x89u, RdnaOpcode::DsAndSrc2B32, 1, 32, false, false, false},
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{0x8au, RdnaOpcode::DsOrSrc2B32, 1, 32, false, false, false},
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{0x8bu, RdnaOpcode::DsXorSrc2B32, 1, 32, false, false, false},
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{0x8du, RdnaOpcode::DsWriteSrc2B32, 1, 32, false, false, false},
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{0x92u, RdnaOpcode::DsMinSrc2F32, 1, 32, false, false, false},
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{0x93u, RdnaOpcode::DsMaxSrc2F32, 1, 32, false, false, false},
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{0x95u, RdnaOpcode::DsAddSrc2F32, 1, 32, false, false, false},
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{0x01u, RdnaOpcode::DsSubU32, 1, 32, false, false, false},
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{0x05u, RdnaOpcode::DsMinI32, 1, 32, false, false, false},
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{0x06u, RdnaOpcode::DsMaxI32, 1, 32, false, false, false},
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@ -554,6 +570,29 @@ bool isDsAtomicOpcode(RdnaOpcode opcode) {
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}
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}
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bool isDsSrc2Opcode(RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::DsAddSrc2U32:
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case RdnaOpcode::DsSubSrc2U32:
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case RdnaOpcode::DsRsubSrc2U32:
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case RdnaOpcode::DsIncSrc2U32:
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case RdnaOpcode::DsDecSrc2U32:
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case RdnaOpcode::DsMinSrc2I32:
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case RdnaOpcode::DsMaxSrc2I32:
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case RdnaOpcode::DsMinSrc2U32:
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case RdnaOpcode::DsMaxSrc2U32:
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case RdnaOpcode::DsAndSrc2B32:
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case RdnaOpcode::DsOrSrc2B32:
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case RdnaOpcode::DsXorSrc2B32:
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case RdnaOpcode::DsWriteSrc2B32:
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case RdnaOpcode::DsMinSrc2F32:
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case RdnaOpcode::DsMaxSrc2F32:
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case RdnaOpcode::DsAddSrc2F32:
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return true;
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default: return false;
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}
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}
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std::uint32_t dsSourceCount(RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::DsWrxchg2RtnB32:
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@ -975,6 +1014,12 @@ RdnaInstruction DecodeRdnaDs(std::uint32_t programCounter, std::span<const std::
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} else if (instruction.op == RdnaOpcode::DsWrite2st64B64 || instruction.op == RdnaOpcode::DsRead2st64B64 || instruction.op == RdnaOpcode::DsWrxchg2st64RtnB64) {
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instruction.memoryOffset = offset0 * 512u;
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instruction.secondaryOffset = offset1 * 512u;
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} else if (isDsSrc2Opcode(instruction.op)) {
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if ((offset1 & 0x80u) != 0u) {
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throw std::runtime_error("DS src2 operation with the offset taken from the address is not supported");
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}
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instruction.memoryOffset = 0u;
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instruction.secondaryOffset = signExtend(combinedOffset & 0x7fffu, 15u) * 4u;
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}
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instruction.destination = d16Half(vectorRegister(vdst), instruction.op);
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@ -116,6 +116,7 @@ private:
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bool dsRead2(const RdnaInstruction& inst);
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bool dsWrite(const RdnaInstruction& inst);
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bool dsWrite2(const RdnaInstruction& inst);
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bool dsSrc2(const RdnaInstruction& inst, IrOpcode opcode);
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bool dsAtomic2(const RdnaInstruction& inst, IrOpcode opcode, bool returnsValue);
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bool dsAtomic64(const RdnaInstruction& inst, IrOpcode opcode, bool returnsValue);
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bool dsCondxchg32(const RdnaInstruction& inst);
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@ -339,6 +339,38 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
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return dsAtomic(inst, IrOpcode::SharedAtomicXor32, false);
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case RdnaOpcode::DsXorRtnB32:
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return dsAtomic(inst, IrOpcode::SharedAtomicXor32, true);
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case RdnaOpcode::DsAddSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicIAdd32);
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case RdnaOpcode::DsSubSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicISub32);
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case RdnaOpcode::DsRsubSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicRsub32);
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case RdnaOpcode::DsIncSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicInc32);
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case RdnaOpcode::DsDecSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicDec32);
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case RdnaOpcode::DsMinSrc2I32:
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return dsSrc2(inst, IrOpcode::SharedAtomicSMin32);
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case RdnaOpcode::DsMaxSrc2I32:
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return dsSrc2(inst, IrOpcode::SharedAtomicSMax32);
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case RdnaOpcode::DsMinSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicUMin32);
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case RdnaOpcode::DsMaxSrc2U32:
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return dsSrc2(inst, IrOpcode::SharedAtomicUMax32);
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case RdnaOpcode::DsAndSrc2B32:
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return dsSrc2(inst, IrOpcode::SharedAtomicAnd32);
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case RdnaOpcode::DsOrSrc2B32:
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return dsSrc2(inst, IrOpcode::SharedAtomicOr32);
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case RdnaOpcode::DsXorSrc2B32:
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return dsSrc2(inst, IrOpcode::SharedAtomicXor32);
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case RdnaOpcode::DsWriteSrc2B32:
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return dsSrc2(inst, IrOpcode::WriteSharedU32);
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case RdnaOpcode::DsMinSrc2F32:
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return dsSrc2(inst, IrOpcode::SharedAtomicFMin32);
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case RdnaOpcode::DsMaxSrc2F32:
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return dsSrc2(inst, IrOpcode::SharedAtomicFMax32);
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case RdnaOpcode::DsAddSrc2F32:
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return dsSrc2(inst, IrOpcode::SharedAtomicFAdd32);
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case RdnaOpcode::DsWrxchgRtnB32:
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return dsAtomic(inst, IrOpcode::SharedAtomicSwap32, true);
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@ -194,6 +194,23 @@ bool TranslationContext::dsWrite2(const RdnaInstruction& inst) {
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return true;
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||||
}
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||||
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||||
bool TranslationContext::dsSrc2(const RdnaInstruction& inst, IrOpcode opcode) {
|
||||
if (inst.gds) {
|
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throw std::runtime_error("GDS src2 operations are not supported");
|
||||
}
|
||||
const MemoryInfo memory = sharedMemoryInfoFromInstruction(inst);
|
||||
const IrU32 address = readU32(inst.source0);
|
||||
MemoryInfo source = memory;
|
||||
source.offset = memory.secondaryOffset;
|
||||
source.secondaryOffset = 0u;
|
||||
IrValue* value = loadSharedU32(1u, address, source, inst.programCounter);
|
||||
MemoryInfo target = memory;
|
||||
target.secondaryOffset = 0u;
|
||||
IrValue& active = ir.GetExec();
|
||||
(void)ir.Emit(opcode, IrOpcodeType(opcode), {&address.Value(), value, &active}, addMemoryInfo(target, inst.programCounter));
|
||||
return true;
|
||||
}
|
||||
|
||||
bool TranslationContext::dsAtomic2(const RdnaInstruction& inst, IrOpcode opcode, bool returnsValue) {
|
||||
const MemoryInfo memory = sharedMemoryInfoFromInstruction(inst);
|
||||
const IrU32 address = readU32(inst.source0);
|
||||
|
|
|
|||
|
|
@ -328,6 +328,7 @@ Throughout the project, every function at every stage either **does exactly what
|
|||
- [Min/max S# reduction](../../core/libs/prx/libSceAgcDriver/Graphics/src/GuestSamplerResource.cpp) (libSceAgcDriver) - `FILTER_MODE` 1 and 2 use Vulkan's min and max reduction (the same `SQ_IMG_FILTER_MODE` values RADV programs). Measured on RDNA2 (gfx1035), not on the console: only texels of non-zero weight are reduced, and the weight is taken after rounding to the 8-bit subtexel grid (a sample within 1/512 texel of a centre reduces that texel alone); a driver with other `subTexelPrecisionBits` reduces a different set there. Gathers ignore the mode.
|
||||
- [Min/max S#](../../core/libs/prx/libSceAgcDriver/Graphics/src/GuestSamplerResource.cpp) (libSceAgcDriver, shader recompiler) - throws with anisotropy, a linear mip filter, depth or color-texture compare, or bilinear filtering of an image the recompiler point-samples (sint, converted, depth-bits).
|
||||
- [Raw `buffer_load_dwordx2`](../../core/shader/recompiler/SpirvBackend/src/SpirvMemory/SpirvMemoryInstructions.cpp) is one 64-bit access on the hardware (with or without glc), so it never sees half of a `buffer_atomic_swap_x2`. Only a glc load that is 8-byte aligned and in bounds, in a program that has the 64-bit storage view (it uses 64-bit buffer atomics), is read with one 64-bit atomic load; every other dwordx2 load is two dword loads and can tear against a concurrent 64-bit write: loads without glc, and loads in a program without 64-bit buffer atomics while another shader writes the pair with `swap_x2`.
|
||||
- [DS src2 operations](../../core/shader/recompiler/Translation/src/MemoryInstructions/SharedMemoryInstructions.cpp) (`ds_*_src2_*`, GFX10.1 only) read `DS[B]`, with `B = A + 4 * sext(offset1[6:0]:offset0)`, and then update `DS[A]` with the matching 32-bit atomic, so the read of `B` is not atomic with the update of `A`. The form that takes the offset from the address (`offset1[7]` set), the 64-bit forms and GDS throw: whether the LDS address keeps `A[31:17]` in that form, and whether the 64-bit forms scale the offset by 4 or 8, is not documented.
|
||||
- [wcsrtombs_s](../../core/libs/prx/libc/src/Multibyte.cpp) (libc) follows the console's `libc.prx`, but a runtime-constraint violation only returns its error: the default handler there writes the message and a newline to `stderr` before returning, which is not done here. Conversion uses the C locale of `wcrtomb` (`MB_CUR_MAX` 1), so the path where a multibyte character does not fit the remaining space is not reached
|
||||
- [The narrow printf family](../../core/libs/prx/libc/src/Formatting.cpp) (libc) passes `%ls` and `%S` to glibc on Linux, which reads them as strings of 32-bit `wchar_t`; the guest's `wchar_t` is 16 bits (UTF-16), so these conversions fail with -1. The Windows path converts them to UTF-8, and `guest_formatting` checks wide conversions on Windows only
|
||||
- [collate<char>::_Getcat](../../core/libs/prx/libc/src/LocaleSupport.cpp) (libc) builds the facet for the C locale only and throws for any other locale name. The console's `libc.prx` stores pointers to its collation state tables at offsets 0x10 and 0x18 of the facet; ours leaves them null, as only the facet's own functions read them. `do_transform` throws for input with embedded null characters, which the console drops depending on the output buffer size, and for results of 4095 characters or more, whose string storage uses the guest's over-aligned large allocation.
|
||||
|
|
|
|||
Loading…
Reference in New Issue