Merge pull request #70 from SamG-Coder/main
fix(shader): support scalar bit operations and 64-bit SAVEEXEC
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commit
cdc95d9a70
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@ -114,14 +114,17 @@ enum class RdnaOpcode : std::uint16_t {
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ExpParam,
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Unknown,
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Unsupported,
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SCmovB32,
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SCmovB64,
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SAbsI32,
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SAbsdiffI32,
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SBrevB32,
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SSextI32I8,
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SSextI32I16,
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SBcnt0I32B32,
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SBcnt1I32B32,
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SBcnt1I32B64,
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SFf0I32B32,
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SFf1I32B32,
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SFf1I32B64,
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SFlbitI32B32,
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@ -135,6 +138,9 @@ enum class RdnaOpcode : std::uint16_t {
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SOrn2SaveexecB32,
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SAndn1SaveexecB32,
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SAndSaveexecB64,
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SOrSaveexecB64,
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SXorSaveexecB64,
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SAndn2SaveexecB64,
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SOrn2SaveexecB64,
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SAndn1SaveexecB64,
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SNotB32,
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@ -36,14 +36,17 @@ bool IsScalarAluOpcode(RdnaOpcode opcode) {
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case RdnaOpcode::SCmpLtI32:
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case RdnaOpcode::SCmpGtI32:
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case RdnaOpcode::SCmpEqU32:
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case RdnaOpcode::SCmovB32:
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case RdnaOpcode::SCmovB64:
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case RdnaOpcode::SAbsI32:
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case RdnaOpcode::SAbsdiffI32:
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case RdnaOpcode::SBrevB32:
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case RdnaOpcode::SSextI32I8:
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case RdnaOpcode::SSextI32I16:
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case RdnaOpcode::SBcnt0I32B32:
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case RdnaOpcode::SBcnt1I32B32:
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case RdnaOpcode::SBcnt1I32B64:
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case RdnaOpcode::SFf0I32B32:
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case RdnaOpcode::SFf1I32B32:
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case RdnaOpcode::SFf1I32B64:
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case RdnaOpcode::SFlbitI32B32:
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@ -54,6 +57,9 @@ bool IsScalarAluOpcode(RdnaOpcode opcode) {
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case RdnaOpcode::SOrn2SaveexecB32:
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case RdnaOpcode::SAndn1SaveexecB32:
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case RdnaOpcode::SAndSaveexecB64:
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case RdnaOpcode::SOrSaveexecB64:
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case RdnaOpcode::SXorSaveexecB64:
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case RdnaOpcode::SAndn2SaveexecB64:
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case RdnaOpcode::SOrn2SaveexecB64:
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case RdnaOpcode::SAndn1SaveexecB64:
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case RdnaOpcode::SNotB32:
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@ -11,14 +11,17 @@ RdnaOpcode decodeSop1Opcode(std::uint32_t opcode) {
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switch (opcode) {
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case 0x03u: return RdnaOpcode::SMovB32;
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case 0x04u: return RdnaOpcode::SMovB64;
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case 0x05u: return RdnaOpcode::SCmovB32;
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case 0x06u: return RdnaOpcode::SCmovB64;
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case 0x07u: return RdnaOpcode::SNotB32;
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case 0x08u: return RdnaOpcode::SNotB64;
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case 0x09u: return RdnaOpcode::SWqmB32;
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case 0x0au: return RdnaOpcode::SWqmB64;
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case 0x0bu: return RdnaOpcode::SBrevB32;
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case 0x0du: return RdnaOpcode::SBcnt0I32B32;
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case 0x0fu: return RdnaOpcode::SBcnt1I32B32;
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case 0x10u: return RdnaOpcode::SBcnt1I32B64;
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case 0x11u: return RdnaOpcode::SFf0I32B32;
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case 0x13u: return RdnaOpcode::SFf1I32B32;
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case 0x14u: return RdnaOpcode::SFf1I32B64;
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case 0x15u: return RdnaOpcode::SFlbitI32B32;
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@ -32,6 +35,9 @@ RdnaOpcode decodeSop1Opcode(std::uint32_t opcode) {
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case 0x1fu: return RdnaOpcode::SGetpcB64;
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case 0x20u: return RdnaOpcode::SSetpcB64;
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case 0x24u: return RdnaOpcode::SAndSaveexecB64;
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case 0x25u: return RdnaOpcode::SOrSaveexecB64;
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case 0x26u: return RdnaOpcode::SXorSaveexecB64;
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case 0x27u: return RdnaOpcode::SAndn2SaveexecB64;
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case 0x28u: return RdnaOpcode::SOrn2SaveexecB64;
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case 0x2du: return RdnaOpcode::SQuadmaskB64;
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case 0x34u: return RdnaOpcode::SAbsI32;
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@ -196,6 +202,9 @@ std::uint32_t scalarDestinationDwordCount(RdnaOpcode opcode) {
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case RdnaOpcode::SBitset1B64:
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case RdnaOpcode::SGetpcB64:
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case RdnaOpcode::SAndSaveexecB64:
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case RdnaOpcode::SOrSaveexecB64:
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case RdnaOpcode::SXorSaveexecB64:
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case RdnaOpcode::SAndn2SaveexecB64:
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case RdnaOpcode::SOrn2SaveexecB64:
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case RdnaOpcode::SQuadmaskB64:
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case RdnaOpcode::SAndn1SaveexecB64:
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@ -28,6 +28,7 @@ void TranslationContext::sSaveexec(const RdnaInstruction& inst, IrOpcode operati
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// Callers name the lane-wise operation; the exec mask words themselves combine bitwise.
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if (operation == IrOpcode::LogicalAnd) operation = IrOpcode::BitwiseAnd32;
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else if (operation == IrOpcode::LogicalOr) operation = IrOpcode::BitwiseOr32;
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else if (operation == IrOpcode::LogicalXor) operation = IrOpcode::BitwiseXor32;
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const bool writeFirst = SaveexecWritesDestinationFirst();
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if (write64) {
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const std::array<IrU32, 2> oldExec{IrU32(ir.GetExecLo()), IrU32(ir.GetExecHi())};
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@ -40,6 +40,13 @@ bool TranslationContext::emitScalar(const RdnaInstruction& inst) {
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case RdnaOpcode::SCselectB64:
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scalarSelect64(inst, sourceAt(inst, 1u));
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return true;
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case RdnaOpcode::SCmovB32: {
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const IrU32 source = readU32(sourceAt(inst, 0u));
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const IrU32 previous = readU32(inst.destination);
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const IrU32 result(ir.Select(ir.GetScc(), source.Value(), previous.Value()));
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writeRawU32(inst.destination, result);
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return true;
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}
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case RdnaOpcode::SCmovB64:
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scalarSelect64(inst, inst.destination);
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return true;
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@ -61,6 +68,15 @@ bool TranslationContext::emitScalar(const RdnaInstruction& inst) {
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case RdnaOpcode::SAndSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, false, true);
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return true;
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case RdnaOpcode::SOrSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalOr, false, false, true);
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return true;
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case RdnaOpcode::SXorSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalXor, false, false, true);
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return true;
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case RdnaOpcode::SAndn2SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, true, false, true);
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return true;
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case RdnaOpcode::SAndn1SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, true, true);
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return true;
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@ -195,6 +211,18 @@ bool TranslationContext::emitScalar(const RdnaInstruction& inst) {
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writeOperand(inst.destination, &result);
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return true;
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}
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case RdnaOpcode::SBcnt0I32B32:
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case RdnaOpcode::SFf0I32B32: {
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const IrU32 source = readU32(sourceAt(inst, 0u));
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auto& inverted = ir.BitwiseNot(source.Value());
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const bool count = inst.op == RdnaOpcode::SBcnt0I32B32;
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auto& result = ir.Emit(count ? IrOpcode::BitCount32 : IrOpcode::FindILsb32, IrType::U32, {&inverted});
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writeOperand(inst.destination, &result);
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if (count) {
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ir.SetScc(ir.INotEqual(result, ir.Constant(0u)));
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}
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return true;
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}
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case RdnaOpcode::SBcnt1I32B32:
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return simpleInteger(inst, IrOpcode::BitCount32, IrType::U32, false, false, true);
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case RdnaOpcode::SBcnt1I32B64:
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