Merge pull request #1253 from popcoder565/feat/shader-system-opcodes
feat(shader): decode halt, trap return, code end, GWS and ordered count instructions
This commit is contained in:
Adrià
GitHub
commit
e28fa01ca6
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@ -288,6 +288,20 @@ target_link_libraries(agc_masked_select_tests PRIVATE shader_recompiler_agc_driv
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set_target_properties(agc_masked_select_tests PROPERTIES CXX_EXTENSIONS OFF)
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configure_windows_unwind(agc_masked_select_tests)
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add_test_executable(agc_wave_control_decode_tests EXCLUDE_FROM_ALL tests/WaveControlDecode.cpp)
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target_include_directories(agc_wave_control_decode_tests PRIVATE ${LIBS_INCLUDE_DIR})
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target_link_libraries(agc_wave_control_decode_tests PRIVATE shader_recompiler_agc_driver libc)
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set_target_properties(agc_wave_control_decode_tests PROPERTIES CXX_EXTENSIONS OFF)
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configure_windows_unwind(agc_wave_control_decode_tests)
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if(BUILD_TESTING)
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set_target_properties(agc_wave_control_decode_tests PROPERTIES EXCLUDE_FROM_ALL OFF)
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add_test(NAME agc_wave_control_decode COMMAND agc_wave_control_decode_tests)
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if(WIN32)
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set_tests_properties(agc_wave_control_decode PROPERTIES ENVIRONMENT_MODIFICATION
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"PATH=path_list_prepend:$<TARGET_FILE_DIR:libc>")
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endif()
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endif()
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add_test_executable(agc_vop1_control_decode_tests EXCLUDE_FROM_ALL tests/Vop1ControlDecode.cpp)
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target_link_libraries(agc_vop1_control_decode_tests PRIVATE shader_recompiler_agc_driver libc)
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set_target_properties(agc_vop1_control_decode_tests PROPERTIES CXX_EXTENSIONS OFF)
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@ -0,0 +1,137 @@
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#include "RdnaDecoder/RdnaInstructionDecoder.hpp"
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#include "Recompiler.hpp"
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#include <array>
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#include <cstdio>
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#include <exception>
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#include <stdexcept>
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#include <string>
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#include <string_view>
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#include <tuple>
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#include <vector>
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namespace {
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using namespace ShaderRecompiler;
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void require(bool condition, const std::string& message) {
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if (!condition) throw std::runtime_error(message);
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}
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bool isVector(const RdnaOperand& operand, std::uint32_t reg) {
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return operand.kind == RdnaOperandKind::VectorRegister && operand.reg == reg;
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}
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void verifyDecode() {
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const std::vector<std::uint32_t> code{
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0xbf8d0000u, 0xbf8d0001u, 0xbf911234u, 0xbe802204u,
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0xd8661234u, 0x00000001u, 0xd86a0000u, 0x00000000u, 0xd86e0000u, 0x00000002u,
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0xd8720000u, 0x00000000u, 0xd8620000u, 0x00000000u, 0xd8760000u, 0x00000003u,
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0xd8fe0004u, 0x05000001u,
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0xbf9f0000u, 0xbf9f0000u, 0xffffffffu,
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};
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const auto program = RdnaInstructionDecoder{}.Decode(code);
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const auto& decoded = program.instructions;
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require(decoded.size() == 12u, "decoding did not stop at the first s_code_end: " + std::to_string(decoded.size()) + " instructions");
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require(decoded[0].op == RdnaOpcode::SSethalt && decoded[0].source0.value == 0u && decoded[0].sourceCount == 1u, "s_sethalt 0");
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require(decoded[1].op == RdnaOpcode::SSethalt && decoded[1].source0.value == 1u, "s_sethalt 1");
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require(decoded[2].op == RdnaOpcode::SSendmsghalt && decoded[2].source0.value == 0x1234u && decoded[2].sourceCount == 1u, "s_sendmsghalt 0x1234");
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require(decoded[3].op == RdnaOpcode::SRfeB64 && decoded[3].destination.kind == RdnaOperandKind::Null && decoded[3].sourceCount == 1u &&
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decoded[3].source0.kind == RdnaOperandKind::ScalarRegister && decoded[3].source0.reg == 4u, "s_rfe_b64 s[4:5]");
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const std::array<std::tuple<RdnaOpcode, std::uint32_t, std::uint32_t, const char*>, 6> gws{{
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{RdnaOpcode::DsGwsInit, 1u, 0x1234u, "ds_gws_init v1 offset:4660 gds"},
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{RdnaOpcode::DsGwsSemaV, 0u, 0u, "ds_gws_sema_v gds"},
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{RdnaOpcode::DsGwsSemaBr, 1u, 0u, "ds_gws_sema_br v2 gds"},
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{RdnaOpcode::DsGwsSemaP, 0u, 0u, "ds_gws_sema_p gds"},
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{RdnaOpcode::DsGwsSemaReleaseAll, 0u, 0u, "ds_gws_sema_release_all gds"},
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{RdnaOpcode::DsGwsBarrier, 1u, 0u, "ds_gws_barrier v3 gds"},
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}};
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const std::array<std::uint32_t, 6> dataRegisters{1u, 0u, 2u, 0u, 0u, 3u};
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for (std::size_t index = 0; index < gws.size(); ++index) {
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const auto& [opcode, sources, offset, name] = gws[index];
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const auto& instruction = decoded[4u + index];
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require(instruction.op == opcode && instruction.gds && instruction.sourceCount == sources && instruction.memoryOffset == offset &&
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instruction.destination.kind == RdnaOperandKind::None && instruction.wordCount == 2u, name);
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if (sources != 0u) require(isVector(instruction.source0, dataRegisters[index]), std::string(name) + " reads the wrong data register");
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}
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const auto& ordered = decoded[10];
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require(ordered.op == RdnaOpcode::DsOrderedCount && ordered.gds && ordered.memoryOffset == 4u && isVector(ordered.destination, 5u) &&
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isVector(ordered.source0, 1u) && ordered.sourceCount == 1u, "ds_ordered_count v5, v1 offset:4 gds");
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require(decoded[11].op == RdnaOpcode::SCodeEnd, "s_code_end");
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}
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std::string recompile(std::span<const std::uint32_t> code) {
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const std::array<std::uint32_t, 4> userData{0x10000000u, 0x00100000u, 0x40u, 0x00027facu};
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const std::array<std::uint32_t, 2> capabilities{1u, 61u};
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const std::array<std::string_view, 1> extensions{"SPV_KHR_storage_buffer_storage_class"};
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RecompileRequest request{};
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request.shader = {ShaderStage::Compute, 0x20000u, code, 0, {}};
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request.context.waveSize = 64;
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request.context.userDataBaseRegister = 0;
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request.context.userData = userData;
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request.context.compute = ShaderComputeStageInfo{{64u, 1u, 1u}, 0u, {false, false, false}, false, 1u};
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request.target.vulkanVersion = 0x00403000u;
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request.target.spirvVersion = 0x00010600u;
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request.target.subgroupSize = 64u;
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request.target.bdaAbiVersion = 1;
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request.target.supportedCapabilities = capabilities;
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request.target.supportedExtensions = extensions;
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request.target.maxWorkgroupSize = {1024u, 1024u, 64u};
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request.target.maxWorkgroupInvocations = 1024;
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request.target.maxWorkgroupSharedMemoryBytes = 49152;
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request.layout = {0, 0, 0, 128};
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request.useCache = false;
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try {
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const auto result = Recompile(request);
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require(!result.spirv.empty(), "no SPIR-V");
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} catch (const std::exception& error) {
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return error.what();
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}
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return {};
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}
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std::vector<std::uint32_t> withStore(std::initializer_list<std::uint32_t> words) {
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std::vector<std::uint32_t> code(words);
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code.insert(code.end(), {0x7e020281u, 0xe0700000u, 0x80000100u, 0xbf810000u});
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return code;
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}
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void verifyTranslation() {
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require(recompile(withStore({0xbf8d0000u})).empty(), "s_sethalt 0 is refused: " + recompile(withStore({0xbf8d0000u})));
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const std::vector<std::uint32_t> trailingLoop{0x7e020281u, 0xbf820003u, 0xe0700000u, 0x80000100u, 0xbf810000u, 0xbf82fffcu, 0xbf9f0000u, 0xbf9f0000u, 0xffffffffu};
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require(recompile(trailingLoop).empty(), "a program padded with s_code_end after its last branch is refused: " + recompile(trailingLoop));
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const std::vector<std::tuple<std::string_view, std::vector<std::uint32_t>, std::string_view>> refused{
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{"s_sethalt 1", withStore({0xbf8d0001u}), "s_sethalt 1 at pc 0 halts the wave"},
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{"s_sendmsghalt", withStore({0xbf910001u}), "s_sendmsghalt 1 at pc 0 halts the wave"},
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{"s_code_end", {0x7e020281u, 0xbf9f0000u}, "s_code_end at pc 4 is reached"},
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{"s_rfe_b64", withStore({0xbe802204u}), "s_rfe_b64 at pc 0 returns from a trap handler"},
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{"ds_gws_init", withStore({0xd8660000u, 0x00000001u}), "ds_gws_init at pc 0: global wave sync"},
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{"ds_gws_sema_v", withStore({0xd86a0000u, 0x00000000u}), "ds_gws_sema_v at pc 0: global wave sync"},
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{"ds_gws_sema_br", withStore({0xd86e0000u, 0x00000002u}), "ds_gws_sema_br at pc 0: global wave sync"},
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{"ds_gws_sema_p", withStore({0xd8720000u, 0x00000000u}), "ds_gws_sema_p at pc 0: global wave sync"},
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{"ds_gws_sema_release_all", withStore({0xd8620000u, 0x00000000u}), "ds_gws_sema_release_all at pc 0: global wave sync"},
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{"ds_gws_barrier", withStore({0xd8760000u, 0x00000003u}), "ds_gws_barrier at pc 0: global wave sync"},
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{"ds_ordered_count", withStore({0xd8fe0000u, 0x05000001u}), "ds_ordered_count at pc 0: GDS counters"},
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};
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for (const auto& [name, code, message] : refused) {
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const auto error = recompile(code);
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require(error.find(message) != std::string::npos, std::string(name) + ": expected a refusal with '" + std::string(message) + "', got '" + error + "'");
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}
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}
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}
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int main() {
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try {
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verifyDecode();
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verifyTranslation();
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std::puts("wave control decode tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::fprintf(stderr, "%s\n", error.what());
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}
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return 1;
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}
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@ -0,0 +1,92 @@
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#include "prx/libSceAgcDriver/Execution/include/VulkanDevice.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/Draw.hpp"
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#include "Recompiler.hpp"
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#include "VulkanTestDevice.hpp"
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#include <algorithm>
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#include <array>
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#include <cstdint>
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#include <cstdio>
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#include <iostream>
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#include <string>
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#include <vector>
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namespace {
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using AgcDriver::Graphics::Require;
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using ShaderRecompiler::ShaderStage;
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constexpr std::uint32_t Threads = 32;
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constexpr std::uint32_t Inputs = 4;
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constexpr std::uint32_t Results = 16;
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alignas(256) std::array<std::uint32_t, Threads * Inputs> Input{};
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alignas(256) std::array<std::uint32_t, Threads * Results> Output{};
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alignas(256) constexpr std::array<std::uint32_t, 16> Code{
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0x34020084, 0x34060086, 0xe0301000, 0x80000401, 0xbf8c3f70, 0xbf8d0000, 0x4a0a0881, 0xbf820003,
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0xe0701000, 0x80010503, 0xbf810000, 0xbf82fffc, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000,
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};
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void Fill(std::uint32_t tid, std::uint32_t* words) { words[0] = tid * 0x01010101u + 7u; }
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std::array<std::uint32_t, 4> BufferDescriptor(const void* data, std::uint32_t bytes) {
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const auto address = reinterpret_cast<std::uintptr_t>(data);
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return {static_cast<std::uint32_t>(address), static_cast<std::uint32_t>((address >> 32u) & 0xffffu), bytes, 0x01016facu};
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}
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std::string Hex(std::uint32_t value) {
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char text[16];
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std::snprintf(text, sizeof(text), "0x%08x", value);
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return text;
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}
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void Expect(std::uint32_t tid, std::uint32_t actual, std::uint32_t expected, const char* name) {
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Require(actual == expected, std::string("scalar sethalt: lane ") + std::to_string(tid) + " " + name + " is " + Hex(actual) + ", expected " + Hex(expected));
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}
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void Run(AgcDriver::VulkanDevice& device) {
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for (std::uint32_t tid = 0; tid < Threads; ++tid) Fill(tid, &Input[tid * Inputs]);
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Output.fill(0xdeadbeefu);
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std::vector<std::uint32_t> userData(8, 0u);
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const auto input = BufferDescriptor(Input.data(), static_cast<std::uint32_t>(Input.size() * 4u));
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const auto output = BufferDescriptor(Output.data(), static_cast<std::uint32_t>(Output.size() * 4u));
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std::copy(input.begin(), input.end(), userData.begin());
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std::copy(output.begin(), output.end(), userData.begin() + 4);
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const std::span<const std::uint32_t> code(Code);
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const std::array<ShaderRecompiler::MemoryRegion, 1> memory{{{reinterpret_cast<std::uintptr_t>(code.data()), std::as_bytes(code)}}};
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const ShaderRecompiler::ShaderComputeStageInfo compute{{Threads, 1, 1}, 0u, {false, false, false}, false, 1};
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ShaderRecompiler::RecompileRequest request{
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{ShaderStage::Compute, reinterpret_cast<std::uintptr_t>(code.data()), code, 0, {}},
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{32, 0, userData, compute, std::nullopt, std::nullopt, memory},
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device.Target(),
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{0, 0, 0, 128}
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};
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request.useCache = false;
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const auto result = ShaderRecompiler::Recompile(request);
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device.Dispatch(result, 1, 1, 1, {}, reinterpret_cast<std::uintptr_t>(code.data()));
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device.WaitIdle();
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}
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void Check() {
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for (std::uint32_t tid = 0; tid < Threads; ++tid) {
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const std::uint32_t* in = &Input[tid * Inputs];
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const std::uint32_t* out = &Output[tid * Results];
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Expect(tid, out[0], in[0] + 1u, "store after s_sethalt 0");
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Expect(tid, out[1], 0xdeadbeefu, "word after the store");
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}
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}
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}
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int main() {
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try {
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const auto device = OpenVulkanTestDevice();
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if (!device) return VulkanTestSkipped;
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Run(*device);
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Check();
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std::puts("scalar sethalt tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@ -1042,6 +1042,17 @@ enum class RdnaOpcode : std::uint16_t {
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Exp,
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VMulHiI32I24,
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VMulHiU32U24,
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SSethalt,
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SSendmsghalt,
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SCodeEnd,
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SRfeB64,
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DsGwsInit,
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DsGwsSemaV,
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DsGwsSemaBr,
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DsGwsSemaP,
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DsGwsSemaReleaseAll,
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DsGwsBarrier,
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DsOrderedCount,
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Count
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};
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@ -168,7 +168,7 @@ void DecodeRdnaProgram(std::span<const std::uint32_t> code, RdnaProgram& program
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furthestBranchTarget = std::max(furthestBranchTarget, targetIndex);
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}
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if (instruction.op == RdnaOpcode::SEndpgm && furthestBranchTarget < wordIndex) {
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if ((instruction.op == RdnaOpcode::SEndpgm || instruction.op == RdnaOpcode::SCodeEnd) && furthestBranchTarget < wordIndex) {
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return;
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}
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}
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@ -234,6 +234,12 @@ constexpr MemoryOpcodeInfo dsOpcodes[] = {
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{0x11u, RdnaOpcode::DsCmpstF32, 1, 32, false, false, false},
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{0x14u, RdnaOpcode::DsNop, 1, 32, false, false, false},
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{0x15u, RdnaOpcode::DsAddF32, 1, 32, false, false, false},
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{0x18u, RdnaOpcode::DsGwsSemaReleaseAll, 1, 32, false, false, false},
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{0x19u, RdnaOpcode::DsGwsInit, 1, 32, false, false, false},
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{0x1au, RdnaOpcode::DsGwsSemaV, 1, 32, false, false, false},
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{0x1bu, RdnaOpcode::DsGwsSemaBr, 1, 32, false, false, false},
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{0x1cu, RdnaOpcode::DsGwsSemaP, 1, 32, false, false, false},
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{0x1du, RdnaOpcode::DsGwsBarrier, 1, 32, false, false, false},
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{0x22u, RdnaOpcode::DsRsubRtnU32, 1, 32, false, false, false},
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{0x2cu, RdnaOpcode::DsMskorRtnB32, 1, 32, false, false, false},
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{0x30u, RdnaOpcode::DsCmpstRtnB32, 1, 32, false, false, false},
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@ -316,6 +322,7 @@ constexpr MemoryOpcodeInfo dsOpcodes[] = {
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{0x3cu, RdnaOpcode::DsReadU16, 1, 16, false, false, false},
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{0x3du, RdnaOpcode::DsConsume, 1, 32, false, false, false},
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{0x3eu, RdnaOpcode::DsAppend, 1, 32, false, false, false},
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{0x3fu, RdnaOpcode::DsOrderedCount, 1, 32, false, false, false},
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{0x4du, RdnaOpcode::DsWriteB64, 2, 32, false, false, false},
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{0x4eu, RdnaOpcode::DsWrite2B64, 4, 32, false, false, false},
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{0x4fu, RdnaOpcode::DsWrite2st64B64, 4, 32, false, false, false},
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@ -469,6 +476,18 @@ bool isDsWriteOpcode(RdnaOpcode opcode) {
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}
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}
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bool isDsGwsOpcode(RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::DsGwsInit:
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case RdnaOpcode::DsGwsSemaV:
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case RdnaOpcode::DsGwsSemaBr:
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case RdnaOpcode::DsGwsSemaP:
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case RdnaOpcode::DsGwsSemaReleaseAll:
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case RdnaOpcode::DsGwsBarrier: return true;
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default: return false;
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}
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}
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bool isDsAtomicOpcode(RdnaOpcode opcode) {
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switch (opcode) {
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case RdnaOpcode::DsAddU32:
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@ -565,7 +584,10 @@ std::uint32_t dsSourceCount(RdnaOpcode opcode) {
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case RdnaOpcode::DsBpermuteB32: return 2u;
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case RdnaOpcode::DsReadAddtidB32:
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case RdnaOpcode::DsConsume:
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case RdnaOpcode::DsAppend: return 0u;
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case RdnaOpcode::DsAppend:
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case RdnaOpcode::DsGwsSemaV:
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case RdnaOpcode::DsGwsSemaP:
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case RdnaOpcode::DsGwsSemaReleaseAll: return 0u;
|
||||
default: return isDsWriteOpcode(opcode) || isDsAtomicOpcode(opcode) ? 2u : 1u;
|
||||
}
|
||||
}
|
||||
|
|
@ -960,6 +982,9 @@ RdnaInstruction DecodeRdnaDs(std::uint32_t programCounter, std::span<const std::
|
|||
instruction.source1 = isDsWriteOpcode(instruction.op) ? d16Half(vectorRegister(data0), instruction.op) : vectorRegister(data0);
|
||||
instruction.source2 = vectorRegister(data1);
|
||||
instruction.sourceCount = dsSourceCount(instruction.op);
|
||||
if (isDsGwsOpcode(instruction.op)) {
|
||||
instruction.destination.kind = RdnaOperandKind::None;
|
||||
}
|
||||
return instruction;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ RdnaOpcode decodeSop1Opcode(std::uint32_t opcode) {
|
|||
case 0x1eu: return RdnaOpcode::SBitset1B64;
|
||||
case 0x1fu: return RdnaOpcode::SGetpcB64;
|
||||
case 0x20u: return RdnaOpcode::SSetpcB64;
|
||||
case 0x22u: return RdnaOpcode::SRfeB64;
|
||||
case 0x24u: return RdnaOpcode::SAndSaveexecB64;
|
||||
case 0x25u: return RdnaOpcode::SOrSaveexecB64;
|
||||
case 0x26u: return RdnaOpcode::SXorSaveexecB64;
|
||||
|
|
@ -204,9 +205,11 @@ RdnaOpcode decodeSoppOpcode(std::uint32_t opcode) {
|
|||
case 0x0au: return RdnaOpcode::SBarrier;
|
||||
case 0x0bu: return RdnaOpcode::SEndpgm;
|
||||
case 0x0cu: return RdnaOpcode::SWaitcnt;
|
||||
case 0x0du: return RdnaOpcode::SSethalt;
|
||||
case 0x0eu: return RdnaOpcode::SSleep;
|
||||
case 0x0fu: return RdnaOpcode::SSetprio;
|
||||
case 0x10u: return RdnaOpcode::SSendmsg;
|
||||
case 0x11u: return RdnaOpcode::SSendmsghalt;
|
||||
case 0x12u: return RdnaOpcode::STrap;
|
||||
case 0x13u: return RdnaOpcode::SIcacheInv;
|
||||
case 0x14u: return RdnaOpcode::SIncperflevel;
|
||||
|
|
@ -218,6 +221,7 @@ RdnaOpcode decodeSoppOpcode(std::uint32_t opcode) {
|
|||
case 0x1au: return RdnaOpcode::SCbranchCdbg;
|
||||
case 0x1bu:
|
||||
case 0x1eu: return RdnaOpcode::SEndpgm;
|
||||
case 0x1fu: return RdnaOpcode::SCodeEnd;
|
||||
case 0x20u: return RdnaOpcode::SInstPrefetch;
|
||||
case 0x21u: return RdnaOpcode::SClause;
|
||||
case 0x22u: return RdnaOpcode::SWaitIdle;
|
||||
|
|
@ -242,7 +246,8 @@ bool isSoppWaitOpcode(RdnaOpcode opcode) {
|
|||
opcode == RdnaOpcode::STrap || opcode == RdnaOpcode::STtracedata || opcode == RdnaOpcode::SInstPrefetch ||
|
||||
opcode == RdnaOpcode::SClause || opcode == RdnaOpcode::SCbranchCdbg || opcode == RdnaOpcode::SIcacheInv ||
|
||||
opcode == RdnaOpcode::SIncperflevel || opcode == RdnaOpcode::SDecperflevel || opcode == RdnaOpcode::SWaitIdle ||
|
||||
opcode == RdnaOpcode::SRoundMode || opcode == RdnaOpcode::SDenormMode;
|
||||
opcode == RdnaOpcode::SRoundMode || opcode == RdnaOpcode::SDenormMode || opcode == RdnaOpcode::SSethalt ||
|
||||
opcode == RdnaOpcode::SSendmsghalt;
|
||||
}
|
||||
|
||||
std::uint32_t scalarDestinationDwordCount(RdnaOpcode opcode) {
|
||||
|
|
@ -340,7 +345,7 @@ RdnaInstruction DecodeRdnaSop1(std::uint32_t programCounter, std::span<const std
|
|||
instruction.destination = DecodeRdnaScalarDestination(scalarDestination, programCounter);
|
||||
return instruction;
|
||||
}
|
||||
if (instruction.op == RdnaOpcode::SSetpcB64) {
|
||||
if (instruction.op == RdnaOpcode::SSetpcB64 || instruction.op == RdnaOpcode::SRfeB64) {
|
||||
instruction.sourceCount = 1;
|
||||
instruction.destination.kind = RdnaOperandKind::Null;
|
||||
instruction.source0 = DecodeRdnaScalarSource(scalarSource0, programCounter);
|
||||
|
|
|
|||
|
|
@ -5,6 +5,22 @@
|
|||
|
||||
namespace ShaderRecompiler {
|
||||
|
||||
namespace {
|
||||
|
||||
const char* globalWaveSyncName(RdnaOpcode opcode) {
|
||||
switch (opcode) {
|
||||
case RdnaOpcode::DsGwsInit: return "ds_gws_init";
|
||||
case RdnaOpcode::DsGwsSemaV: return "ds_gws_sema_v";
|
||||
case RdnaOpcode::DsGwsSemaBr: return "ds_gws_sema_br";
|
||||
case RdnaOpcode::DsGwsSemaP: return "ds_gws_sema_p";
|
||||
case RdnaOpcode::DsGwsSemaReleaseAll: return "ds_gws_sema_release_all";
|
||||
case RdnaOpcode::DsGwsBarrier: return "ds_gws_barrier";
|
||||
default: throw std::logic_error("opcode is not a global wave sync instruction");
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void TranslateMemoryInstruction(IrBuilder& builder, const RdnaInstruction& instruction) {
|
||||
throw std::runtime_error("TranslateMemoryInstruction not implemented");
|
||||
}
|
||||
|
|
@ -445,6 +461,15 @@ bool TranslationContext::emitMemory(const RdnaInstruction& inst) {
|
|||
return dsAppendConsume(inst, IrOpcode::DataConsume);
|
||||
case RdnaOpcode::DsAppend:
|
||||
return dsAppendConsume(inst, IrOpcode::DataAppend);
|
||||
case RdnaOpcode::DsGwsInit:
|
||||
case RdnaOpcode::DsGwsSemaV:
|
||||
case RdnaOpcode::DsGwsSemaBr:
|
||||
case RdnaOpcode::DsGwsSemaP:
|
||||
case RdnaOpcode::DsGwsSemaReleaseAll:
|
||||
case RdnaOpcode::DsGwsBarrier:
|
||||
throw std::runtime_error(std::string(globalWaveSyncName(inst.op)) + " at pc " + std::to_string(inst.programCounter) + ": global wave sync barriers and semaphores shared by waves of different workgroups are not modeled");
|
||||
case RdnaOpcode::DsOrderedCount:
|
||||
throw std::runtime_error("ds_ordered_count at pc " + std::to_string(inst.programCounter) + ": GDS counters updated in wave launch order are not modeled");
|
||||
case RdnaOpcode::DsWriteAddtidB32:
|
||||
return dsAddtid(inst, true);
|
||||
case RdnaOpcode::DsReadAddtidB32:
|
||||
|
|
|
|||
|
|
@ -417,6 +417,18 @@ bool TranslationContext::emitScalar(const RdnaInstruction& inst) {
|
|||
return true;
|
||||
case RdnaOpcode::SDenormMode:
|
||||
throw std::runtime_error("s_denorm_mode " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + ": the recompiler does not model denormal modes");
|
||||
case RdnaOpcode::SSethalt:
|
||||
if ((inst.source0.value & 1u) != 0u) {
|
||||
throw std::runtime_error("s_sethalt " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + " halts the wave until a debugger resumes it");
|
||||
}
|
||||
emitControlNop();
|
||||
return true;
|
||||
case RdnaOpcode::SSendmsghalt:
|
||||
throw std::runtime_error("s_sendmsghalt " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + " halts the wave until a debugger resumes it");
|
||||
case RdnaOpcode::SCodeEnd:
|
||||
throw std::runtime_error("s_code_end at pc " + std::to_string(inst.programCounter) + " is reached: it marks the end of the code and raises an illegal instruction exception");
|
||||
case RdnaOpcode::SRfeB64:
|
||||
throw std::runtime_error("s_rfe_b64 at pc " + std::to_string(inst.programCounter) + " returns from a trap handler, and recompiled shaders run without one");
|
||||
case RdnaOpcode::SWaitcntDepctr:
|
||||
case RdnaOpcode::SWaitIdle:
|
||||
emitWaitcnt();
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ Throughout the project, every function at every stage either **does exactly what
|
|||
- [sceRtcParseDateTime](../../core/libs/prx/libSceRtc/Export.cpp) (libSceRtc) - accepted format assumed to be the ISO 8601 subset `YYYY-MM-DDTHH:MM:SS[.ffffff]` (T/t/space separator, optional fractional seconds) with the sibling RFC 3339 zone suffix (`Z` or `±HH:MM`), plus the RFC 2822 shape `Ddd, DD Mon YYYY HH:MM:SS[ GMT| ±HHMM]` and the asctime shape `Ddd Mon DD HH:MM:SS YYYY` (day zero- or space-padded) that shadPS4 parses at fixed positions; the weekday name is not checked against the date, a `±HHMM` offset is subtracted to get UTC like the RFC 3339 path (shadPS4 adds it), a string without a zone is taken as UTC, and anything outside these shapes throws instead of returning a parse error, unverified against hardware
|
||||
- [sceAudio3dPortOpen](../../core/libs/prx/libSceAudio3d/Export.cpp) (libSceAudio3d) - buffer modes 0 and 1 (also selected by the 0x10 and 0x18 parameter sizes) and 3 beds depend on an SDK version check in the module ([prosper](https://github.com/mattias800/prosper)) and throw. A repeated `sceAudio3dInitialize` (`NOT_READY` in shadPS4, 0 in prosper) and `sceAudio3dPortAdvance` on a full queue (`NOT_READY` in shadPS4, unhandled in KytyPS5) throw too
|
||||
- [sceAudio3dObjectReserve](../../core/libs/prx/libSceAudio3d/Export.cpp) (libSceAudio3d) - object ids, the `max_objects` limit and the checks of `sceAudio3dObjectReserve` and `sceAudio3dObjectUnreserve` follow [shadPS4](https://github.com/shadps4-emu/shadPS4) (PS4), the only reference with a body: ids count up from 1 per port, skipping 0, 0xFFFFFFFF and ids in use, and a failed reserve writes 0xFFFFFFFF
|
||||
- [s_sethalt](../../core/shader/recompiler/Translation/src/ScalarInstructions.cpp) (core/shader/recompiler) - with SIMM16[0] clear it is a no-op: the RDNA 2 ISA guide describes that value as resuming a halted wave, and a wave that executes it is not halted; measured on a gfx1035 (RDNA 2) wave: `s_sethalt 0` followed by a VALU op completes and gives the normal result. Only SIMM16[0] is read; with it set the instruction throws
|
||||
- [AMPR WriteAddressFromCounterPairOnCompletion](../../core/libs/prx/libSceAmpr/Export.cpp) (libSceAmpr) - the pair of an even counter n is assumed to give counter n in the low 32 bits and n + 1 in the high 32 bits. Wait compare values, wait flush and counter index ranges follow the [ampr_emu](https://github.com/drakmor/ampr_emu) reimplementation; the flush is accepted and has no effect, as commands run in order
|
||||
- [AMPR command sizes](../../core/libs/prx/libSceAmpr/Export.cpp) (libSceAmpr) - commands use the emulator's own encoding with an 8-byte header, so `Nop(n)` takes 8 + 4n bytes where the console record is n dwords including its header (`NopWithData(n)`: (n + 1) dwords). The measure functions agree with the appended sizes, but a title that pads to an exact offset or the end of the buffer with `Nop(remaining / 4)` gets `SCE_AMPR_ERROR_BUFFER_FULL` or a shifted offset. The at-start flag of the `_04_00` writes is ignored; commands run in order, each after the previous one completes
|
||||
- [AMPR counter access](../../core/libs/prx/libkernel/Apr/src/Apr.cpp) (libSceAmpr) - signatures and checks of `WaitOnCounter_04_00`, `WriteCounter_04_00`, `ConstructNop` and `ConstructMarker` taken from the [ampr_emu](https://github.com/drakmor/ampr_emu) reimplementation, which hands counter commands to the console and does not show their effect. The counters are taken as 32 bits each: the 8-byte access of counter n spans n (low) and n + 1 (high), the 2- and 1-byte accesses select a half or a byte of the counter by its offset, waits compare at the access width (signed and wrapped compares included), the AND mask applies to both sides and the atomic writes wrap within the access. The `ConstructNop` type is not recorded
|
||||
|
|
|
|||
Loading…
Reference in New Issue