Merge pull request #295 from MichonGoddijn231849/split/pixel-ancillary
fix(shader): packed pixel ancillary as SampleId and Layer, gl_Layer via Geometry, Z export formats
This commit is contained in:
Adrià
GitHub
commit
e2b527bb09
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@ -788,6 +788,14 @@ if(BUILD_TESTING)
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set_tests_properties(image_sample_gather PROPERTIES ENVIRONMENT_MODIFICATION
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"PATH=path_list_prepend:$<TARGET_FILE_DIR:libc>")
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endif()
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add_test_executable(pixel_ancillary_tests ${LIBS_INCLUDE_DIR}/tests/PixelAncillary.cpp)
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target_link_libraries(pixel_ancillary_tests PRIVATE shader_recompiler_agc_driver libc)
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configure_windows_unwind(pixel_ancillary_tests)
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add_test(NAME pixel_ancillary COMMAND pixel_ancillary_tests)
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if(WIN32)
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set_tests_properties(pixel_ancillary PROPERTIES ENVIRONMENT_MODIFICATION
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"PATH=path_list_prepend:$<TARGET_FILE_DIR:libc>")
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endif()
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add_test_executable(guest_indexed_draw_tests ${LIBS_INCLUDE_DIR}/tests/GuestIndexedDraw.cpp)
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target_include_directories(guest_indexed_draw_tests PRIVATE ${LIBS_INCLUDE_DIR})
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target_link_libraries(guest_indexed_draw_tests PRIVATE libSceAgc libSceAgcDriver libc)
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@ -894,6 +894,10 @@ VulkanDevice::VulkanDevice(const PresentationWindow* window) : state(std::make_u
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if (enabled.shaderImageGatherExtended) state->capabilities.push_back(spv::CapabilityImageGatherExtended);
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enabled.shaderResourceMinLod = available.shaderResourceMinLod;
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if (enabled.shaderResourceMinLod) state->capabilities.push_back(spv::CapabilityMinLod);
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enabled.sampleRateShading = available.sampleRateShading;
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enabled.geometryShader = available.geometryShader;
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if (enabled.geometryShader) state->capabilities.push_back(spv::CapabilityGeometry);
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enabled.shaderClipDistance = available.shaderClipDistance;
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if (enabled.shaderStorageImageWriteWithoutFormat) state->capabilities.push_back(spv::CapabilityStorageImageWriteWithoutFormat);
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if (enabled.shaderStorageImageReadWithoutFormat) state->capabilities.push_back(spv::CapabilityStorageImageReadWithoutFormat);
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// Bindless image tables index an image array with a wave-uniform runtime slot.
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@ -72,6 +72,19 @@ constexpr std::uint32_t ScreenOffsetMask = ~0x01ff01ffu;
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// Bits 26/27 (ZCLIP_NEAR/FAR_DISABLE) become depth clamping; bit 19 selects the [0, 1] clip space.
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constexpr std::uint32_t ClipControlMask = ~(0x80000u | 0x01000000u | 0x0c000000u);
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bool zFormatSupported(std::uint32_t format) {
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return format == 0u || format == 1u || format == 2u || format == 3u || format == 9u;
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}
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std::uint32_t shaderControlMask(std::uint32_t zFormat) {
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constexpr std::uint32_t zExportEnable = 0x1u;
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constexpr std::uint32_t maskExportEnable = 0x100u;
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auto mask = ShaderControlMask;
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if (zFormat != 0u && zFormatSupported(zFormat)) mask &= ~zExportEnable;
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if (zFormat == 9u) mask &= ~maskExportEnable;
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return mask;
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}
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// Debug aid: APS5_IGNORE_DEPTH_TEST=1 renders depth- and stencil-tested draws without a depth
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// target as if their tests always passed (wrong occlusion, but the draws run), so stages that
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// depth-test everything can exercise the draw paths before depth targets exist.
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@ -469,7 +482,7 @@ State DecodeState(const QueueState& queue) {
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Require((depthControl & 8u) == 0 || result.depth.has_value(), "depth bounds without a depth surface");
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Require((depthControl & 0xc0000000u) == 0, "depth-conditional color writes are unsupported");
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}
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zero(cx, 0x203, ShaderControlMask, "depth export, shader coverage or ordered fragment execution");
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zero(cx, 0x203, shaderControlMask(read(cx, 0x1c4)), "depth export, shader coverage or ordered fragment execution");
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zero(cx, 0x2dc, AlphaToCoverageMask, "alpha-to-coverage");
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zero(cx, 0x2f8, ~0u, "multisampling or coverage conversion");
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zero(cx, 0x292, ScanModeMask, "scan conversion mode");
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@ -515,7 +528,7 @@ State DecodeState(const QueueState& queue) {
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// CB_COLOR_CONTROL mode 0 disables color writes, which only matters when a target is written.
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if (const auto colorControl = read(cx, 0x202); !colorControlSupported(colorControl, result.hasColorTarget)) throw std::runtime_error(colorControlMessage(colorControl));
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zero(cx, 0x1c4, ~0u, "depth or sample-mask export");
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zero(cx, 0x1c4, zFormatSupported(read(cx, 0x1c4)) ? 0u : ~0u, "depth or sample-mask export");
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const auto exportFormat = result.hasColorTarget ? read(cx, 0x1c5) : 0u;
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APS5_LOG_OUT_DEBUG("Export format=%u", exportFormat);
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// SPI_SHADER_POS_FORMAT: POS0 must be a 4-component position; later vectors carry the misc/clip
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@ -758,7 +771,9 @@ std::string DrawRejection(const QueueState& queue, bool indexed) {
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if (auto reason = require((word & 8u) == 0 || surface, "depth bounds without a depth surface"); !reason.empty()) return reason;
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if (auto reason = require((word & 0xc0000000u) == 0, "depth-conditional color writes are unsupported"); !reason.empty()) return reason;
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}
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if (auto reason = nonzero(cx, 0x203, ShaderControlMask, "depth export, shader coverage or ordered fragment execution"); !reason.empty()) return reason;
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std::uint32_t zFormat = 0;
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static_cast<void>(value(cx, 0x1c4, zFormat));
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if (auto reason = nonzero(cx, 0x203, shaderControlMask(zFormat), "depth export, shader coverage or ordered fragment execution"); !reason.empty()) return reason;
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if (auto reason = nonzero(cx, 0x2dc, AlphaToCoverageMask, "alpha-to-coverage"); !reason.empty()) return reason;
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if (auto reason = nonzero(cx, 0x2f8, ~0u, "multisampling or coverage conversion"); !reason.empty()) return reason;
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if (auto reason = nonzero(cx, 0x292, ScanModeMask, "scan conversion mode"); !reason.empty()) return reason;
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@ -775,7 +790,7 @@ std::string DrawRejection(const QueueState& queue, bool indexed) {
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if (auto reason = nonzero(cx, 0x204, ClipControlMask, "unsupported PA_CL_CLIP_CNTL flags"); !reason.empty()) return reason;
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std::uint32_t targetMask = 0, shaderMask = 0;
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if (value(cx, 0x8e, targetMask) && value(cx, 0x8f, shaderMask) && value(cx, 0x202, word) && !colorControlSupported(word, (targetMask & shaderMask) != 0)) return colorControlMessage(word);
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if (auto reason = nonzero(cx, 0x1c4, ~0u, "depth or sample-mask export"); !reason.empty()) return reason;
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if (auto reason = nonzero(cx, 0x1c4, zFormatSupported(zFormat) ? 0u : ~0u, "depth or sample-mask export"); !reason.empty()) return reason;
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if (PixelProgramUnset(queue)) return NullPixelProgramRejection(queue);
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for (const auto offset : {0x1b3u, 0x1b4u, 0x1c5u}) {
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if (find(cx, offset) != cx.end()) continue;
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@ -582,6 +582,35 @@ void DepthStencilTests() {
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expectFailure([&] { AgcDriver::Graphics::DecodeState(queue); }, "DCC 3D color targets");
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}
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// SPI_SHADER_Z_FORMAT (0x1c4) and the export enables of DB_SHADER_CONTROL (0x203): Z export needs a
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// format with a depth channel (1, 2, 3 or 32_ABGR 9), the sample mask needs 32_ABGR, and the
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// formats the export path does not lay out are refused. A missing 0x1c4 gives no verdict here.
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void ZExportTests() {
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constexpr std::uint32_t zExportEnable = 0x1u;
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constexpr std::uint32_t maskExportEnable = 0x100u;
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const auto withExports = [](std::uint32_t format, std::uint32_t exports) {
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auto queue = makeState();
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queue.context[0x1b3] = 2;
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queue.context[0x1b4] = 2;
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queue.context[0x1c4] = format;
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queue.context[0x203] = 0x800u | exports;
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return queue;
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};
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for (const std::uint32_t format : {1u, 2u, 3u, 9u}) {
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const auto queue = withExports(format, zExportEnable);
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Require(AgcDriver::Graphics::DrawRejection(queue, true).empty(), "a Z export with format " + std::to_string(format) + " was rejected");
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}
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Require(!AgcDriver::Graphics::DrawRejection(withExports(0, zExportEnable), true).empty(), "a Z export without a Z format was accepted");
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Require(AgcDriver::Graphics::DrawRejection(withExports(9, zExportEnable | maskExportEnable), true).empty(), "a sample-mask export with 32_ABGR was rejected");
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Require(!AgcDriver::Graphics::DrawRejection(withExports(1, zExportEnable | maskExportEnable), true).empty(), "a sample-mask export with 32_R was accepted");
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for (std::uint32_t format = 4; format <= 8; ++format) {
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Require(!AgcDriver::Graphics::DrawRejection(withExports(format, 0), true).empty(), "Z format " + std::to_string(format) + " was accepted");
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}
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auto absent = withExports(0, 0);
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absent.context.erase(0x1c4);
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Require(AgcDriver::Graphics::DrawRejection(absent, true).empty(), "a missing SPI_SHADER_Z_FORMAT was rejected (or threw) in the precheck");
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}
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void DepthBoundsBiasTests() {
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const auto bits = [](float value) {
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std::uint32_t word = 0;
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@ -2041,6 +2070,7 @@ int main() {
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hardwareScreenOffsetTests();
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DepthClipTests();
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DepthStencilTests();
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ZExportTests();
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DepthBoundsBiasTests();
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conservativeZExportTests();
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DisabledColorTests();
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@ -0,0 +1,64 @@
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#include "IntermediateRepresentation/IrBuilder.hpp"
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#include "Optimization/ConstantFolder.hpp"
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#include "Optimization/DeadCodeEliminator.hpp"
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#include "Optimization/ShaderInfoCollector.hpp"
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#include <cstdint>
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#include <stdexcept>
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#include <string>
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using namespace ShaderRecompiler;
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static void Require(bool value) { if (!value) throw std::runtime_error("packed pixel ancillary regression"); }
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static IrValue& Build(IrProgram& program, IrOpcode opcode, std::uint32_t offset, std::uint32_t count) {
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program.Resources().stage = IrShaderStage::Pixel;
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program.Resources().resourceTrackingComplete = true;
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auto& block = program.CreateBlock();
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program.SetEntryBlock(block);
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program.BlockOrder().push_back(&block);
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IrBuilder builder(program);
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builder.SetInsertionPoint(block);
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auto& ancillary = builder.Emit(IrOpcode::GetBuiltin, IrType::U32, {&builder.Constant(static_cast<std::uint32_t>(StageInputKind::PackedAncillary)), &builder.Constant(0u)});
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auto& user = opcode == IrOpcode::BitwiseOr32 ? builder.Emit(opcode, IrType::U32, {&ancillary, &builder.Constant(offset)})
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: builder.Emit(opcode, IrType::U32, {&ancillary, &builder.Constant(offset), &builder.Constant(count)});
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static_cast<void>(builder.Emit(IrOpcode::ReferenceU32, IrType::Void, {&user}));
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static_cast<void>(builder.Emit(IrOpcode::Return, IrType::Void, {}));
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return user;
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}
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static void Lower(IrProgram& program) {
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ConstantFolder().Fold(program);
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DeadCodeEliminator().RemoveIdentities(program);
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DeadCodeEliminator().Eliminate(program);
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const ShaderPixelInputInfo pixel {};
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ShaderInfoCollector().Collect(program, ShaderStageInputInfo {nullptr, &pixel, nullptr});
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}
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static void Extract(IrOpcode opcode, std::uint32_t offset, std::uint32_t count, StageInputKind kind, std::uint32_t fieldOffset) {
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IrProgram program;
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auto& user = Build(program, opcode, offset, count);
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Lower(program);
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const IrValue* field = user.Argument(0)->Resolve();
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Require(field->Opcode() == IrOpcode::GetBuiltin);
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Require(static_cast<StageInputKind>(field->Argument(0)->Resolve()->ImmediateU32()) == kind);
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Require(user.Argument(1)->Resolve()->ImmediateU32() == fieldOffset);
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Require(user.Argument(2)->Resolve()->ImmediateU32() == count);
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}
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static void Refused(IrOpcode opcode, std::uint32_t offset, std::uint32_t count) {
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IrProgram program;
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static_cast<void>(Build(program, opcode, offset, count));
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try {
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Lower(program);
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} catch (const std::runtime_error& error) {
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Require(std::string(error.what()).find("unsupported live use") != std::string::npos);
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return;
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}
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Require(false);
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}
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int main() {
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Extract(IrOpcode::BitFieldUExtract, 8u, 4u, StageInputKind::SampleId, 0u);
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Extract(IrOpcode::BitFieldUExtract, 9u, 2u, StageInputKind::SampleId, 1u);
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Extract(IrOpcode::BitFieldUExtract, 16u, 13u, StageInputKind::Layer, 0u);
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Extract(IrOpcode::BitFieldSExtract, 20u, 9u, StageInputKind::Layer, 4u);
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Refused(IrOpcode::BitwiseOr32, 1u, 0u);
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Refused(IrOpcode::BitFieldUExtract, 2u, 4u);
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Refused(IrOpcode::BitFieldUExtract, 10u, 4u);
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Refused(IrOpcode::BitFieldUExtract, 13u, 2u);
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Refused(IrOpcode::BitFieldUExtract, 16u, 14u);
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}
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@ -2,8 +2,11 @@
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#include "IntermediateRepresentation/IrBuilder.hpp"
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#include <algorithm>
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#include <array>
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#include <bit>
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#include <cstdint>
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#include <utility>
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#include <vector>
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namespace ShaderRecompiler {
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namespace {
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@ -181,12 +184,68 @@ bool foldCompositeExtract(IrBuilder& builder, IrValue& inst, IrOpcode construct,
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return false;
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}
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void collectUses(IrValue& value, std::vector<IrUse>& uses) {
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for (const IrUse& use : value.OperandUses()) {
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if (use.user->Opcode() == IrOpcode::Identity) {
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collectUses(*use.user, uses);
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} else {
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uses.push_back(use);
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}
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}
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}
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bool lowerPackedAncillary(IrProgram& program, IrBuilder& builder, IrValue& ancillary) {
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auto& kind = resolveArg(ancillary, 0);
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if (!isImmediate(kind, IrType::U32) || static_cast<StageInputKind>(kind.ImmediateU32()) != StageInputKind::PackedAncillary) {
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return false;
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}
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std::vector<IrUse> uses;
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collectUses(ancillary, uses);
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std::array<IrValue*, 2> fields {};
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const auto field = [&](std::size_t index) -> IrValue& {
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if (fields[index] == nullptr) {
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const auto builtin = index == 0u ? StageInputKind::SampleId : StageInputKind::Layer;
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IrValue& created = program.CreateValue(IrOpcode::GetBuiltin, IrType::U32);
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created.AddArgument(&builder.Constant(static_cast<std::uint32_t>(builtin)));
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created.AddArgument(&builder.Constant(0u));
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ancillary.Parent()->InsertInstructionBefore(&ancillary, &created);
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fields[index] = &created;
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}
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return *fields[index];
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};
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constexpr std::array<std::pair<std::uint32_t, std::uint32_t>, 2> ranges {{{8u, 4u}, {16u, 13u}}};
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bool lowered = false;
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for (const IrUse& use : uses) {
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IrValue& user = *use.user;
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if ((user.Opcode() != IrOpcode::BitFieldUExtract && user.Opcode() != IrOpcode::BitFieldSExtract) || use.operand != 0u) {
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continue;
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}
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auto& offset = resolveArg(user, 1);
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auto& count = resolveArg(user, 2);
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if (!isImmediate(offset, IrType::U32) || !isImmediate(count, IrType::U32) || count.ImmediateU32() == 0u) {
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continue;
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}
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const auto range = std::ranges::find_if(ranges, [&](const auto& candidate) {
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return offset.ImmediateU32() >= candidate.first && count.ImmediateU32() <= candidate.second &&
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offset.ImmediateU32() - candidate.first <= candidate.second - count.ImmediateU32();
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});
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if (range == ranges.end()) {
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continue;
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}
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user.ReplaceArgument(0, &field(static_cast<std::size_t>(range - ranges.begin())));
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user.ReplaceArgument(1, &builder.Constant(offset.ImmediateU32() - range->first));
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lowered = true;
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}
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return lowered;
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}
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} // namespace
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bool ConstantFolder::tryFoldValue(IrProgram& program, IrValue& value) const {
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IrBuilder builder(program);
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switch (value.Opcode()) {
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case IrOpcode::Phi: return foldPhi(value);
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case IrOpcode::GetBuiltin: return lowerPackedAncillary(program, builder, value);
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case IrOpcode::SelectU1:
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case IrOpcode::SelectF32:
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case IrOpcode::SelectU32: return foldSelect(value);
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@ -137,10 +137,13 @@ void DefineModule(SpirvEmitterState& state) {
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if (state.cullDistanceVariable != 0) {
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state.module.EmitCapability(spv::CapabilityCullDistance);
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}
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if (state.layerVariable != 0 || InputVariableForKind(state, StageInputKind::Layer) != 0) {
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if (state.layerVariable != 0) {
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state.module.RequireVersion(0x00010500u);
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state.module.EmitCapability(spv::CapabilityShaderLayer);
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}
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if (InputVariableForKind(state, StageInputKind::Layer) != 0) {
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state.module.EmitCapability(spv::CapabilityGeometry);
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}
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if (state.viewportIndexVariable != 0) {
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state.module.RequireVersion(0x00010500u);
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state.module.EmitCapability(spv::CapabilityShaderViewportIndex);
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