4 Commits

Author	SHA1	Message	Date
ljkx	9d110245fe	feat(relinker): lower register-form INSERTQ ... Lower INSERTQ xmm1, xmm2 (F2 0F 79) out of line with SSE2 only instead of failing the --to-intel relink. Length and index are read from bits 69:64 and 77:72 of the source; dst[127:64] is zeroed as on hardware. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>	2026-09-30 15:18:02 +02:00
Dean Galvin	ff1fa9eb69	feat(relinker): lower register-form EXTRQ and relocate following instructions for short sites ... Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ButHENCbXXt8h4EZuWUabJ	2026-09-28 16:37:15 +13:00
devilismyfriend	01c4e3edf7	feat(relinker): --to-intel lowers SSE4a sites to same-length jumps into an appended stub section ... EXTRQ, INSERTQ, MOVNTSS and MOVNTSD are rewritten at relink time: same-length in-place forms where they exist, otherwise a jmp rel32 into an appended executable section holding a scratch-free SSE body and a jump back, so no code shifts and no RIP-relative or jump-table operand needs adjusting. Decoder fixes for POPCNT and 0F BB (BTC), codegen and elfpatcher tests, README and technical-debt notes. The runtime illegal-instruction trap stays as a fallback. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_0177gthrWEBBfBu5xJDXgBfo	2026-09-26 19:00:39 -07:00
boykopovar	4b643c6655	refactor(core): seprated folders for relinker and libs	2026-09-11 14:53:01 +03:00

Renamed from core/codegen/src/x86/Amd64OnlyInstructionMatcher.cpp (Browse further)