4066e6dd29
test(shader): keep the flat cache bits test within CI's time limit
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 16:54:53 +02:00
4c57426b51
Merge pull request #501 from adriadam10/fix/vop3-legacy-mods
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fix(shader): v_mullit_f32 legacy rules, v_cvt_pk_u8_f32 rounding and VOP3 neg/abs
2026-10-06 02:32:06 +13:00
a2b0e24e9e
Merge pull request #508 from adriadam10/feat/vop3-cube-clamp
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feat(shader): accept clamp on v_cube*_f32 and match their zero and subnormal results
2026-10-06 02:31:22 +13:00
53dc19cf61
Merge pull request #617 from Erige005/test/discard-refused-recompile-results
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test(agc): discard the results of recompiles expected to be refused
2026-10-05 22:16:17 +13:00
f457d87bbd
feat(shader): accept clamp on v_cube*_f32 and match their zero and subnormal results
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 10:57:27 +02:00
7bb6c59e83
fix(shader): v_mullit_f32 legacy rules, v_cvt_pk_u8_f32 rounding and VOP3 neg/abs
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 10:53:50 +02:00
698c23d81e
Merge pull request #528 from adriadam10/test/vop1-vop2-integer
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fix(shader): v_cvt_rpi/flr_i32_f32 NaN and exact round-half-up, VOP1/VOP2 integer test
2026-10-05 21:35:53 +13:00
e3e1dfae16
Merge pull request #526 from adriadam10/test/scalar-sop1
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fix(shader): s_wqm SCC and s_andn{1,2}_wrexec destination, SOP1/SOPC/SOPK execution test
2026-10-05 21:35:11 +13:00
5ad0c99f98
Merge pull request #525 from adriadam10/test/scalar-alu
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fix(shader): s_lshlN_add SCC and s_bfe_[iu]32 fields past bit 31
2026-10-05 21:34:30 +13:00
1e37ed456a
Merge pull request #514 from adriadam10/fix/dpp16-movrels-pk-fmac
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fix(shader): DPP16 operands of v_pk_fmac_f16 and the relative moves
2026-10-05 21:33:48 +13:00
6fd9739d9d
Merge pull request #510 from adriadam10/feat/sdwa-vop2-integer-clamp
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feat(shader): saturate VOP2 integer SDWA results on clamp
2026-10-05 21:33:38 +13:00
070ed19249
Merge pull request #509 from adriadam10/feat/sdwa-vop2-integer
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feat(shader): accept every SDWA selector on VOP2 integer ops
2026-10-05 21:32:55 +13:00
17ef50b681
Merge pull request #504 from adriadam10/feat/vop3-opsel-16
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fix(shader): VOP3 op_sel on v_alignbit/alignbyte_b32 and 16-bit max3/min3/med3
2026-10-05 21:32:13 +13:00
bbedad3b00
Merge pull request #500 from adriadam10/fix/f32-clamp-bits
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fix(shader): clamp f32 results to +0 for NaN and -0
2026-10-05 21:31:31 +13:00
d18fa1367c
Merge pull request #612 from oneandonlydean/perf/recompiler-lds-constant-slots
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perf(recompiler): index lane-strided per-invocation LDS by constant slots
2026-10-05 21:24:42 +13:00
ef88b5be00
Merge pull request #490 from oneandonlydean/fix/agc-views-past-max-mip
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fix(agc): address texture views that start past the surface's last mip
2026-10-05 21:22:36 +13:00
e7bf72d503
Merge pull request #616 from adriadam10/feat/mimg-tfe-lwe
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feat(shader): accept tfe and lwe on MIMG loads, stores and samples
2026-10-05 20:29:00 +13:00
56acdef2f5
Merge pull request #569 from adriadam10/feat/global-store-addtid
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feat(shader): implement global_store_dword_addtid
2026-10-05 20:27:36 +13:00
033ac78439
Merge pull request #563 from adriadam10/feat/vop3-mad64-clamp
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feat(shader): implement clamp on v_mad_u64_u32 and v_mad_i64_i32
2026-10-05 20:26:55 +13:00
fb16cb3b19
test(agc): discard the results of recompiles expected to be refused
2026-10-05 07:12:32 +00:00
d044384a89
feat(shader): implement global_store_dword_addtid
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Decode FLAT opcode 0x17 in the global segment and store the data VGPR of
each active lane at the SGPR pair base plus the signed offset plus four
times the lane id, sharing the address path of global_load_dword_addtid.
Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 08:41:19 +02:00
1cc11cee57
feat(shader): accept tfe and lwe on MIMG loads, stores and samples
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 08:25:57 +02:00
31af5a9d22
perf(recompiler): index lane-strided per-invocation LDS by constant slots
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Stages without workgroup memory keep LDS in a per-invocation Function
array. With the array sized to the addresses it reaches (#586 ),
PPSA21564's intro pixel shader still takes 864 bytes of local memory
per thread on NVIDIA: its accesses are lane * 4 + {0, 256, 512}, so
the index stays dynamic and the 192-dword array lives in local memory.
When every LDS access's address is lane * stride + constant (lane id,
constants, adds, multiplies and left shifts), with one stride, a whole
number of dwords, for all of them and no wrap (the bound analysis
already proves that), the emitter now addresses each access by its
constant plus its instruction offset. The lane id is the same for
every access of an invocation, so taking lane * stride out maps the
addresses one to one, keeps which accesses alias and keeps every
access in bounds; the array sees only constant indices and the driver
keeps it in registers. Shaders with any other address form are
emitted as before.
2026-10-05 18:18:29 +13:00
3655c2ae34
Merge pull request #506 from adriadam10/feat/global-atomics-float
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feat(shader): implement the float and 64-bit inc/dec flat and global atomics
2026-10-05 18:15:22 +13:00
2afc403a04
Merge pull request #495 from adriadam10/feat/flat-cache-bits
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feat(shader): accept the glc, slc and dlc cache bits on flat, global and scratch
2026-10-05 18:14:41 +13:00
12cf58256f
Merge pull request #491 from adriadam10/feat/global-atomics
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feat(shader): implement the integer flat and global atomics
2026-10-05 18:13:59 +13:00
50e7712002
Merge pull request #608 from adriadam10/test/scalar-program-flow
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fix(shader): wave-wide exec and vcc branch conditions
2026-10-05 18:13:07 +13:00
f809199b0a
Merge pull request #606 from adriadam10/fix/permlane16-inactive-source
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fix(shader): keep v_permlane16 lanes whose source lane is inactive
2026-10-05 18:12:26 +13:00
e074483ab7
Merge pull request #604 from adriadam10/fix/smem-buffer-offset-overflow
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fix(shader): return zero when an s_buffer_load offset passes 2^32
2026-10-05 18:11:43 +13:00
e90d2edf54
Merge pull request #596 from adriadam10/fix/vop3-pack-ldexp-bits
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fix(shader): compute v_cvt_pknorm_*_f32, v_ldexp_f32 and v_pack_b32_f16 on the bits
2026-10-05 18:11:01 +13:00
bdd10f1929
Merge pull request #475 from adriadam10/feat/mimg-coarse-g16
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feat(shader): implement image_sample_cd/_g16 variants and fix a16 gradient layout
2026-10-05 18:10:20 +13:00
71f248ad54
Merge pull request #568 from adriadam10/fix/f32-minmax-nan
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fix(shader): return src0 when both f32 min/max sources are NaN
2026-10-05 18:09:38 +13:00
4ca60c434c
Merge pull request #524 from DotDebian/feat/mimg-bvh64-intersect-ray
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feat(shader): implement image_bvh64_intersect_ray
2026-10-05 18:08:57 +13:00
1e0f62e118
Merge pull request #515 from adriadam10/fix/dpp16-inactive-source
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fix(shader): DPP16 lanes whose source lane is inactive
2026-10-05 18:08:46 +13:00
a84d759dd2
Merge pull request #498 from adriadam10/feat/vop2-dpp-sdwa-float-mods
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feat(shader): accept float modifiers on v_cndmask_b32, v_mul_legacy_f32 and v_ldexp_f16
2026-10-05 18:08:04 +13:00
0087fb6369
Merge pull request #567 from adriadam10/fix/f32-omod-zero
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fix(shader): apply the f32 output modifier on the bits like the hardware
2026-10-05 18:07:22 +13:00
dbfdcb1c79
Merge pull request #537 from adriadam10/test/vop1-float-unary
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fix(shader): choose unary f32/f16 special results on the bits, as RDNA does
2026-10-05 18:06:40 +13:00
9f5fac08c8
Merge pull request #323 from adriadam10/fix/f16-result-clamp
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fix(shader): apply clamp but not omod to f16 results, as RDNA does
2026-10-05 18:06:29 +13:00
c6df07e604
feat(shader): accept clamp on v_div_fmas/fixup and omod on their f64 forms
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 05:19:06 +02:00
e91eecc402
Merge pull request #607 from adriadam10/test/setpc
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fix(shader): refuse s_setpc_b64 after s_sub with the immediate first
2026-10-05 16:10:53 +13:00
3aedbbc128
Merge pull request #605 from adriadam10/test/ds-swizzle
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test(shader): execute ds_swizzle_b32 in all three offset modes
2026-10-05 16:10:11 +13:00
c67634a15c
feat(shader): implement the float and 64-bit inc/dec flat and global atomics
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 05:05:10 +02:00
183a0f09b4
feat(shader): accept the glc, slc and dlc cache bits on flat, global and scratch
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Loads and stores with glc or dlc are coherent, as MUBUF already does; slc
is a cache hint and changes no result. Atomics keep glc as the return bit.
lds, segment 3 and scratch atomics still throw.
Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 05:05:10 +02:00
038ded6382
feat(shader): implement the integer flat and global atomics
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 05:05:03 +02:00
be866e4214
feat(shader): store through flat and global addresses
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flat_store_* and global_store_* decoded and translated, but a store whose
segment is not scratch was refused when the SPIR-V was emitted ("writable
FLAT/GLOBAL addresses require GPU ownership tracking").
Such a store now goes through the BDA page table like a store through a
GPU-selected V#: the write lookup needs Write permission, which only a
writable registered range imported in place has, and the written page is
noted for the host to mark GPU-written. Byte and short stores, and dword
stores to an address that is not dword aligned, are stored byte by byte.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-05 05:05:03 +02:00
b5da7d00e4
fix(shader): apply the f32 output modifier on the bits like the hardware
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 05:00:29 +02:00
e58e2f0605
feat(shader): accept float modifiers on v_cndmask_b32, v_mul_legacy_f32 and v_ldexp_f16
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- v_cndmask_b32: neg/abs on DPP; neg/abs applied on the bits, as the hardware does
- v_mul_legacy_f32: neg/abs on DPP and SDWA, clamp/omod on SDWA and VOP3
- v_ldexp_f16: neg/abs on src0 for VOP3, DPP and SDWA; NaN result chosen on the bits
Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 04:59:40 +02:00
a15a21c2c6
feat(shader): implement clamp on v_mad_u64_u32 and v_mad_i64_i32
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 04:59:15 +02:00
aff00b8cde
fix(shader): wave-wide exec and vcc branch conditions
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s_cbranch_execz/execnz/vccz/vccnz test the whole wave mask on hardware,
but the single-lane path branched on each lane's own bit, so inactive
lanes took the other side and diverged in scalar state. Branch on a
wave ballot instead, and execute the untested SOPP ops (cdbg branches,
s_clause, s_inst_prefetch, s_setprio, s_waitcnt_depctr, s_ttracedata)
against values measured on hardware.
Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-05 04:56:35 +02:00
7dcbc18182
Merge pull request #601 from nicolasabosch/test/pixel-lds-pipeline-statistics
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test(agc): validate pixel LDS and expose pipeline statistics
2026-10-05 15:52:43 +13:00
Adrià Franch
Dean
Erige005
Dean Galvin
DotDebian