0e61bedf9a
Merge pull request #4162 from Celegans12/fix/shader-wave64-lane-reductions
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fix(shader): match half-wave reductions over relatively addressed vector registers
2026-10-12 23:54:08 +13:00
2979ae37a3
Merge pull request #4152 from adriadam10/feat/phase-b
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perf(agc): build shader pipeline libraries when shaders are registered
2026-10-12 10:31:42 +02:00
f9b592806c
perf(recompiler): keep the buffer base misalignment specialized in registration form
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
56d5a4985d
perf(recompiler): read the formatted buffer helper's V# words as specialization constants when the format is known
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
60151b66b7
perf(recompiler): keep the format word specialized for buffers accessed with the descriptor's format
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
672e43ca67
perf(recompiler): keep compute shaders specialized; only prebuilt vertex and pixel shaders take the registration form
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
361c7e2024
perf(agc): keep oversized shaders specialized and prebuild libraries on their own thread
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
a326fa84f7
fix(recompiler): give registration results a flattened SRT placeholder
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
67556722e1
perf(recompiler): read vertex attribute component selectors at run time when modules are built at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
7f64d14772
perf(agc): build the shader pipeline libraries when graphics stages are resolved at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
4d0b5c7898
perf(agc): give the fragment stage its own descriptor set when modules are built at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:41 +02:00
baf3437465
perf(recompiler): read depth-compare state and export mappings at run time when modules are built at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:33 +02:00
765ea6a10f
perf(recompiler): keep descriptor heaps uncompacted and read image modes at run time when modules are built at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:32 +02:00
ddb6680667
perf(recompiler): read buffer V# words in the shader when modules are built at registration
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Co-Authored-By: Claude <noreply@anthropic.com>
2026-10-12 09:50:32 +02:00
22d662eda7
fix(agc): export the stencil reference from pixel shaders with VK_EXT_shader_stencil_export
2026-10-12 19:44:41 +13:00
d06c065657
Merge pull request #3895 from CouchRiv/fix-shader-vcmpx-f32-family
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fix(shader): keep f32 denormals in compares when denormals are kept
2026-10-12 19:39:34 +13:00
7f7f961bf8
Merge pull request #3739 from eljackjoestar-cmd/codex/masked-first-lane-proof
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fix(shader): prove masked writes through guarded first-lane reads
2026-10-12 19:39:13 +13:00
0ed0d3c9b6
Merge pull request #4033 from MarcZX100/codex/carry-shader-wqm-live-quad-bit-2548
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fix(shader): fold current s_wqm pixel lane
2026-10-12 18:19:43 +13:00
9db923e907
fix(shader): clip primitives with an all-zero clip position
2026-10-12 06:46:34 +02:00
6d1cee6d3f
Merge pull request #3593 from ahir061/fix/recompiler-prime-shared-mutex
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fix(shader): lock recompiler shared mutexes once when created
2026-10-12 17:30:28 +13:00
c22957f7b0
Merge pull request #3951 from Scramblrrrr/codex/constant-phi-definitions-current-main
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fix(shader): preserve distinct SSA definitions when folding Phi inputs
2026-10-12 17:30:04 +13:00
32cb3fea95
Merge pull request #3932 from CouchRiv/fix-shader-f16-denorm-flush-family
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fix(shader): flush f16 denormals in unary, frexp and conversion ops per the float mode
2026-10-12 17:29:43 +13:00
6b0ce1513d
Merge pull request #4018 from Mouhand-Kaddo/fix/demons-loop-continue
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fix(shader): keep Demon's Souls loop shader valid after optimization
2026-10-12 17:29:21 +13:00
18af217211
Merge pull request #3645 from alfalfa-star/fix/recompiler-mesh-grid-size-sgpr
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fix(recompiler): read NumWorkgroups in every mesh shader so RADV sizes its user data
2026-10-12 17:27:54 +13:00
364d7cf29f
fix(shader): match half-wave reductions over relatively addressed vector registers
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A program that uses v_movrels_b32 or v_movreld_b32 keeps every vector
register from the lowest relatively addressed one up in a per-invocation
window array, so its plain register accesses become LoadVectorWindow and
StoreVectorWindow. The half-wave reduction matcher followed only SSA values,
so a wave64 scan, v_permlanex16_b32 join and lane 31/63 read through that
array threw that lane 63 is outside the 32-lane host subgroup.
The matcher now reads a window load at a constant slot as the value of the
last store to that slot earlier in its block, unless a store at a runtime
slot lies in between; each invocation owns its array, so that is the value
the load returns. A store in another block, or a v_movreld_b32 at a runtime
M0 in between, still throws. This was the only refused lane 32-63 read left
among Ghost of Yotei's wave64 graphics programs (one pixel program).
2026-10-12 02:07:50 +02:00
fded8a7e7f
fix(shader): prove masked writes through guarded first-lane reads
2026-10-12 03:57:04 +04:00
5ec6cff3fa
fix(recompiler): include implicit inputs in relative vector windows
2026-10-11 19:23:00 -04:00
de54527a8b
fix(shader): keep f32 denormals in compares when denormals are kept
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With the f32 denormal field of FLOAT_MODE set to keep, v_cmp_X_f32 and
v_cmpx_X_f32 read a denormal operand as zero: NVIDIA, RADV and lavapipe
all flush denormals in their float compares. Compare the operands as
sign-magnitude integers instead, with NaN handled apart. Compares with
flushed denormals are unchanged. This matches RDNA2 (gfx1036) on 256
operand pairs per opcode, with f32 denormals kept and flushed.
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
2026-10-11 18:51:37 -04:00
3905e7e2c9
Merge pull request #3827 from CouchRiv/fix-shader-combined-cvt-i16-f16-omod
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fix(shader): accept output modifiers on v_cvt_i16_f16 and ignore them as the hardware does
2026-10-12 00:39:20 +02:00
ae7dbfa9cb
Merge pull request #3770 from A-Akhil/fix/shader-sin-cos-series
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fix(shader): take v_sin_f32 and v_cos_f32 from an exact series where the driver's result is more than 4 ulp off
2026-10-12 00:29:31 +02:00
f9e1d2541c
Merge pull request #3750 from fma-rc/feat/shader-subvector-loop
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feat(shader): implement s_subvector_loop_begin and s_subvector_loop_end
2026-10-12 00:28:10 +02:00
33067ca0c7
Merge pull request #3856 from ErenYeager1836/carry/recompiler-vector-window
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perf(recompiler): keep relatively addressed vector registers in a window array
2026-10-12 00:10:58 +02:00
825cbd4106
Merge pull request #3531 from karanvora2599/perf/shader-native-packed-f16
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perf(shader): compute v_pk_add_f16 and v_pk_mul_f16 with native f16 math
2026-10-12 00:10:02 +02:00
e53c30bcdf
Merge pull request #3828 from CouchRiv/fix-shader-combined-pknorm-f16
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fix(shader): accept abs, neg and op_sel source modifiers on v_cvt_pknorm_i16_f16 and v_cvt_pknorm_u16_f16
2026-10-12 00:07:49 +02:00
4b355d4e68
Merge pull request #3825 from kr4y4/fix/shader-dpp8-pk-fmac-f16
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fix(shader): accept DPP8 on v_pk_fmac_f16
2026-10-12 00:07:47 +02:00
12d684f4e6
Merge pull request #3807 from AchrafReyani/fix/shader-srt-signed-less-than-uniform
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fix(shader): accept signed less-than in runtime SRT values
2026-10-12 00:05:43 +02:00
949cd55471
Merge pull request #3785 from MrMha/fix/shader-cache-read-allocation
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fix(shader): handle cache file allocation failures
2026-10-12 00:01:43 +02:00
c4d3b3a743
Merge pull request #3726 from NFSS10/perf/srt-plan-use-replacement
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perf(shader): avoid copying SRT read uses
2026-10-11 23:55:24 +02:00
06664a44cd
Merge pull request #3717 from jweidenh/codex/nvidia-pipeline-replay
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feat(agc): capture and replay compute pipeline compilation
2026-10-11 23:54:52 +02:00
e05a603771
Merge pull request #3668 from CouchRiv/fix-shader-float-compare-clamp
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fix(shader): accept the clamp bit on VOP3 float compares
2026-10-11 23:46:41 +02:00
cbd98bbdc1
Merge pull request #3540 from ivica00/fix/srgb-bilinear-cube-zero
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fix(shader): return 0 for an 8-bit sRGB bilinear cube comparison
2026-10-11 23:45:00 +02:00
f35bcafbee
Merge pull request #3662 from Celegans12/perf/recompiler-iteration-selection-storage
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perf(recompiler): reuse sorted sets for iteration selection merges
2026-10-11 23:44:59 +02:00
097b8d82a5
Merge pull request #3621 from goncalompontes/feat/shader-vop3-interp-f32-e64
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feat(shader): decode GFX10 VOP3-encoded interpolation
2026-10-11 23:44:35 +02:00
fe03a7d126
Merge pull request #3660 from Celegans12/fix/cache-replace-open-windows-files
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fix(cache): replace entries while Windows readers retain old files
2026-10-11 23:44:25 +02:00
aab41deda0
Merge pull request #3541 from MarcZX100/codex/amd-ordered-nan-compare-3536
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fix(shader): handle ordered NaN comparisons
2026-10-11 23:43:11 +02:00
660e24eeac
perf(shader): compute v_pk_add_f16 and v_pk_mul_f16 with native f16 math
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v_pk_add_f16 and v_pk_mul_f16 computed each half in f32 and rounded it
back to f16, then fixed the NaN, FP16_OVFL and clamp results on the
bits. On a device with native f16 that rounds to nearest even and keeps
f16 denormals (the Float16, RoundingModeRTE and DenormPreserve
capabilities that #1252 already checks), the arithmetic is now one
f16vec2 OpFAdd or OpFMul decorated NoContraction, and the same NaN,
FP16_OVFL and clamp rules run on its result bits.
The results don't change. f32 has at least 2 * 11 + 2 significand bits,
so rounding an f16 sum or product to f32 and then to f16 gives the
correctly rounded f16 result. Vulkan requires f16 OpFAdd and OpFMul to
be correctly rounded, the module keeps f16 denormals, and any NaN they
produce is replaced by the NaN the existing rules select.
v_pk_fma_f16 and v_pk_fmac_f16 keep the f32 path: Vulkan gives GLSL Fma
only the precision of OpFMul followed by OpFAdd, so a native f16 Fma
may round twice.
New test agc_driver_packed_float16_native compiles one shader with
packed add, mul, fma and fmac (op_sel, op_sel_hi, neg_lo, neg_hi and
clamp variants) with and without Float16, checks that only add and mul
use f16vec2 math, and compares every result bit for bit on random and
special inputs (zeros, denormals, infinities, NaNs, values near the f16
maximum) in nine float modes.
2026-10-11 23:43:03 +02:00
58d59f6279
fix(shader): fold a lane's s_wqm bit of the starting pixel lanes to true
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Vulkan starts only quads holding a non-helper lane, so the bit is set in every
lane it runs. Stray's pixel shader 0x2012f90000 keeps the packed ancillary
word where that bit is clear, and failed with an unsupported live use.
(cherry picked from commit 2068089b3d75fae55d0994a0916a22bffd7ee2a4)
2026-10-11 21:41:01 +00:00
951fd9afcb
Merge pull request #3590 from karanvora2599/perf/shader-f16-minmax-bits
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perf(shader): pick f16 min, max and med3 results on the bits
2026-10-11 23:39:47 +02:00
7de666a937
Merge pull request #3512 from LeandroLP23/fix/shader-mix-f16-directed-rounding
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fix(shader): round v_fma_mixlo_f16 and v_fma_mixhi_f16 in every f16 rounding mode
2026-10-11 23:36:15 +02:00
e44b7cf78c
Merge pull request #3546 from AlxcBTW/fix/vertex-narrow-wave-entry-2
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fix(recompiler): give wave64 vertex programs on 32-lane hosts a 32-lane s3
2026-10-11 23:33:16 +02:00
Dean
Adrià
Adrià Franch
Dean Galvin
fma-rc
Celegans12
eljackjoestar-cmd
jweidenh
Alex
Karan Vora
ThatsLeo