s_movrels and s_movrelsd_2 read the source register through a chain of
selects keyed on the M0 offset, and the relative destination write is a
select between that value and the old register. When the old register
also appears in the chain, the NVIDIA compiler (RTX 5080, 610.74)
evaluates select(a, select(b, x, y), x) as select(a || b, y, x) instead
of select(a && !b, y, x), so s_movrelsd_2_b32 clobbered s13 whenever the
source offset was 3. Rewriting the select, a branch with a phi, a masked
xor or a small function array all fold back into the same form.
Build the read as an OR of select(offset == k, s[base + k], 0) terms, with
the base register used for offsets outside [1, count) as before. The
result is unchanged, and the select nesting the compiler mishandles no
longer forms.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
- v_cndmask_b32: neg/abs on DPP; neg/abs applied on the bits, as the hardware does
- v_mul_legacy_f32: neg/abs on DPP and SDWA, clamp/omod on SDWA and VOP3
- v_ldexp_f16: neg/abs on src0 for VOP3, DPP and SDWA; NaN result chosen on the bits
Co-Authored-By: Claude <noreply@anthropic.com>
s_lshl1..4_add_u32 never wrote SCC; hardware sets it when the shifted-out
bits or the add carry are non-zero. s_bfe_i32/u32 went through
OpBitField{S,U}Extract, which RADV gets wrong when the width runs past
bit 31; build the field from shifts instead.
Adds an execution test for 38 SOP2 opcodes with hardware-captured results.
Co-Authored-By: Claude <noreply@anthropic.com>
op_sel[1:0] on v_alignbit_b32/v_alignbyte_b32 selects the byte of src2 that
holds the shift, op_sel[2] is ignored and op_sel[3] writes the low 16 result
bits to the high half with the low half zeroed (measured on gfx1035).
v_alignbyte_b32 now uses src2[1:0] only, as the ISA says; values >= 4 gave
a wrong result before. v_max3/min3_{i16,u16} and v_med3_u16 take op_sel like
v_med3_i16 already does.
Co-Authored-By: Claude <noreply@anthropic.com>
Decode VOP3b 0x177 and translate it next to v_mad_u64_u32: the high half of
the product comes from SMulHi, and the carry-out is the sign of the exact
sum (bit 64 of the sign-extended product plus the sign-extended addend), as
measured on RDNA2 hardware.
Co-Authored-By: Claude <noreply@anthropic.com>
Decode VOP3 0x172, 0x173 and 0x175. Each op slides a 4-byte window over the
64-bit src0 and adds the byte SAD against src1 to the matching 16-bit
(pk_u16) or 32-bit (mqsad_u32) field of src2; the mqsad forms skip zero
reference bytes. Sums wrap per field, as measured on RDNA2 hardware.
Co-Authored-By: Claude <noreply@anthropic.com>
Decode and translate v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_i32_i8,
v_dot4_u32_u8, v_dot8_i32_i4, v_dot8_u32_u4 (VOP3P 0x14-0x19) and
v_dot4c_i32_i8 (VOP2 0x0d).
Clamp, neg and the op_sel combinations whose behaviour is not
established throw.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Decode VOP3 0x14d and translate it as the per-byte average of S0 and S1,
rounded up where bit 0 of the matching S2 byte is set and truncated
otherwise.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Decode VOP3 0x15a, 0x15b, 0x15c and 0x171 and translate them as the
unsigned sum of absolute differences over the byte or word fields of
the first two sources, accumulated into the third. v_sad_hi_u8 shifts
the sum into the high half first, v_msad_u8 skips the fields whose
reference byte in the second source is zero.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
s_movrels reads SGPR[src + M0] and s_movreld writes SGPR[dst + M0].
The 64-bit forms align the offset down to even (M0 & ~1), and
s_movrelsd_2_b32 takes the source offset from M0[9:0] and the
destination offset from M0[25:16], as measured on hardware. They use
the same select-over-registers lowering as the vector forms, over the
106 SGPRs. The embedded vertex-fetch scan forgets every tracked SGPR on
a relative write.
Co-Authored-By: Claude <noreply@anthropic.com>
The decoder threw for these SOP1 opcodes. The 64-bit find-first-zero and
signed leading-bit counts reuse the existing 64-bit helpers with a flag;
s_quadmask_b32 is the 32-bit half of s_quadmask_b64. s_bcnt0 and s_quadmask
set SCC to result != 0; the find and leading-bit forms leave it.
Co-Authored-By: Claude <noreply@anthropic.com>
These VOP3 opcodes threw in the decoder. v_add_nc_i32 and v_sub_nc_i32 are
what compilers emit for signed saturating add/sub, so their clamp saturates
to the int32 range. The 16-bit mads honour op_sel on their 16-bit sources;
the u32_u16/i32_i16 forms take a 32-bit addend and write all 32 bits, so
they do not get the 16-bit destination select.
Co-Authored-By: Claude <noreply@anthropic.com>
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