Commit Graph

3 Commits

Author SHA1 Message Date
Josip Parlov c90f85535e refactor(agc): name HV4j+E0MBHE sceAgcCreateInterpolantMapping_0100 2026-10-09 17:25:54 +02:00
boykopovar 6acf4ee0ee test(agc): isolate shader linking and interpolant preparation checks 2026-10-08 17:37:38 +03:00
Celegans12 5e851fbb26 feat(agc): implement the interpolant mapping variant for high-half f16 inputs
PPSA26344 imports libSceAgc NID dbOlWdppb4o, whose name is unknown,
and calls it with the (regs, gs, ps) arguments of
sceAgcCreateInterpolantMapping to fill the 32 SPI_PS_INPUT_CNTL
registers. It is exported as sceAgcUnknownCreateInterpolantMapping.
It differs from sceAgcCreateInterpolantMapping only for inputs that
carry the high f16 half alone (is_f16 2): these take the default bit
and DEFAULT_VAL from the high half, as KytyPS5 does.

Both exports share validation and the register loop. More than 32
pixel shader inputs now throw; before, they were written past the
32-register block. agc_interpolant_mapping covers both exports.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-05 17:51:09 +02:00