485 lines
21 KiB
C++
485 lines
21 KiB
C++
#include "Translation/ScalarInstructions.hpp"
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#include "Translation/TranslationContext.hpp"
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#include <stdexcept>
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#include <string>
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namespace ShaderRecompiler {
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void TranslateScalarInstruction(IrBuilder& builder, const RdnaInstruction& instruction) {
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throw std::runtime_error("TranslateScalarInstruction not implemented");
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}
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bool TranslationContext::emitScalar(const RdnaInstruction& inst) {
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switch (inst.op) {
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case RdnaOpcode::SMovB32:
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case RdnaOpcode::SMovkI32:
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movB32(inst, false);
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return true;
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case RdnaOpcode::SMovB64:
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sMovB64(inst);
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return true;
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case RdnaOpcode::SWqmB32:
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sWqm(inst, false);
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return true;
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case RdnaOpcode::SWqmB64:
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sWqm(inst, true);
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return true;
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case RdnaOpcode::SGetpcB64:
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sGetpcB64(inst);
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return true;
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case RdnaOpcode::SSetpcB64:
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return true;
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case RdnaOpcode::SSwappcB64:
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case RdnaOpcode::SCallB64:
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sSwappcB64(inst);
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return true;
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case RdnaOpcode::SSubvectorLoopBegin:
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sSubvectorLoop(inst, true);
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return true;
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case RdnaOpcode::SSubvectorLoopEnd:
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sSubvectorLoop(inst, false);
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return true;
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case RdnaOpcode::SCselectB32:
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sCselectB32(inst);
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return true;
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case RdnaOpcode::SCselectB64:
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scalarSelectMask64(inst);
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return true;
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case RdnaOpcode::SCmovB32: {
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const IrU32 source = readU32(sourceAt(inst, 0u));
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const IrU32 previous = readU32(inst.destination);
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const IrU32 result(ir.Select(ir.GetScc(), source.Value(), previous.Value()));
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writeRawU32(inst.destination, result);
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return true;
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}
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case RdnaOpcode::SCmovB64:
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scalarSelect64(inst, inst.destination);
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return true;
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case RdnaOpcode::SSetregB32:
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if ((inst.source1.value & 0x3fu) == 1u) {
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throw std::runtime_error("s_setreg_b32 at pc " + std::to_string(inst.programCounter) + " writes MODE from an SGPR: runtime MODE changes are not implemented");
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}
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emitControlNop();
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return true;
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case RdnaOpcode::SVersion:
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emitControlNop();
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return true;
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case RdnaOpcode::SSetregImm32B32: {
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const std::uint32_t field = inst.source1.value;
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const std::uint32_t offset = (field >> 6u) & 0x1fu;
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const std::uint32_t size = ((field >> 11u) & 0x1fu) + 1u;
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const std::uint64_t written = static_cast<std::uint64_t>(inst.source0.value) & ((std::uint64_t{1} << size) - 1u);
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if ((field & 0x3fu) != 1u || offset + size > 4u) {
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throw std::runtime_error("s_setreg_imm32_b32 at pc " + std::to_string(inst.programCounter) + " writes a hardware register field other than the MODE rounding fields");
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}
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const std::uint32_t initial = floatMode.has_value() ? floatMode->floatMode : 0u;
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if (written != ((initial >> offset) & ((1u << size) - 1u))) {
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throw std::runtime_error("s_setreg_imm32_b32 at pc " + std::to_string(inst.programCounter) + " changes the initial MODE rounding fields: runtime MODE changes are not implemented");
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}
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emitControlNop();
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return true;
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}
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case RdnaOpcode::SGetregB32: {
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const std::uint32_t field = inst.source0.value;
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const std::uint32_t offset = (field >> 6u) & 0x1fu;
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const std::uint32_t size = ((field >> 11u) & 0x1fu) + 1u;
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if ((field & 0x3fu) != 1u || offset + size > 4u) {
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throw std::runtime_error("s_getreg_b32 at pc " + std::to_string(inst.programCounter) + " reads hardware register " + std::to_string(field & 0x3fu) + " bits " + std::to_string(offset) + ".." + std::to_string(offset + size - 1u) + ": only the MODE round mode fields are modeled");
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}
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const std::uint32_t initial = floatMode.has_value() ? floatMode->floatMode : 0u;
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writeRawU32(inst.destination, IrU32(ir.Constant((initial >> offset) & ((1u << size) - 1u))));
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return true;
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}
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case RdnaOpcode::SCmovkI32: {
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const IrU32 previous = readU32(inst.destination);
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writeRawU32(inst.destination, IrU32(ir.Select(ir.GetScc(), ir.Constant(inst.source0.value), previous.Value())));
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return true;
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}
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case RdnaOpcode::SWaitcnt:
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emitWaitcnt();
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return true;
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case RdnaOpcode::SAndSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, false, false);
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return true;
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case RdnaOpcode::SOrSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalOr, false, false, false);
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return true;
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case RdnaOpcode::SXorSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalXor, false, false, false);
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return true;
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case RdnaOpcode::SAndn1SaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, true, false);
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return true;
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case RdnaOpcode::SAndn2SaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, true, false, false);
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return true;
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case RdnaOpcode::SOrn1SaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalOr, false, true, false);
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return true;
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case RdnaOpcode::SOrn2SaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalOr, true, false, false);
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return true;
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case RdnaOpcode::SNandSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, false, false, true);
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return true;
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case RdnaOpcode::SNorSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalOr, false, false, false, true);
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return true;
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case RdnaOpcode::SXnorSaveexecB32:
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sSaveexec(inst, IrOpcode::LogicalXor, false, false, false, true);
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return true;
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case RdnaOpcode::SAndn1WrexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, true, false, false, true);
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return true;
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case RdnaOpcode::SAndn2WrexecB32:
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sSaveexec(inst, IrOpcode::LogicalAnd, true, false, false, false, true);
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return true;
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case RdnaOpcode::SAndSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, false, true);
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return true;
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case RdnaOpcode::SOrSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalOr, false, false, true);
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return true;
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case RdnaOpcode::SXorSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalXor, false, false, true);
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return true;
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case RdnaOpcode::SAndn2SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, true, false, true);
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return true;
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case RdnaOpcode::SAndn1SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, true, true);
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return true;
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case RdnaOpcode::SOrn2SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalOr, true, false, true);
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return true;
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case RdnaOpcode::SNandSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, false, true, true);
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return true;
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case RdnaOpcode::SNorSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalOr, false, false, true, true);
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return true;
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case RdnaOpcode::SXnorSaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalXor, false, false, true, true);
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return true;
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case RdnaOpcode::SOrn1SaveexecB64:
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sSaveexec(inst, IrOpcode::LogicalOr, false, true, true);
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return true;
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case RdnaOpcode::SAndn1WrexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, false, true, true, false, true);
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return true;
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case RdnaOpcode::SAndn2WrexecB64:
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sSaveexec(inst, IrOpcode::LogicalAnd, true, false, true, false, true);
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return true;
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case RdnaOpcode::SAddU32:
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addU32(inst, false, false);
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return true;
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case RdnaOpcode::SAddcU32:
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addU32(inst, false, true);
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return true;
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case RdnaOpcode::SSubU32:
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subU32(inst, false, false);
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return true;
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case RdnaOpcode::SSubbU32:
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subbU32(inst, false, false);
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return true;
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case RdnaOpcode::SAbsdiffI32:
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sAbsdiffI32(inst);
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return true;
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case RdnaOpcode::SAddI32:
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sAddSubI32(inst, false);
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return true;
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case RdnaOpcode::SSubI32:
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sAddSubI32(inst, true);
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return true;
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case RdnaOpcode::SLshl1AddU32:
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sLshlAddU32(inst, 1u);
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return true;
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case RdnaOpcode::SLshl2AddU32:
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sLshlAddU32(inst, 2u);
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return true;
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case RdnaOpcode::SLshl3AddU32:
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sLshlAddU32(inst, 3u);
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return true;
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case RdnaOpcode::SLshl4AddU32:
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sLshlAddU32(inst, 4u);
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return true;
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case RdnaOpcode::SMinI32:
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scalarMinMax32(inst, IrOpcode::SMin32, IrOpcode::SLessThan32);
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return true;
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case RdnaOpcode::SMaxI32:
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scalarMinMax32(inst, IrOpcode::SMax32, IrOpcode::SGreaterThan32);
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return true;
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case RdnaOpcode::SMinU32:
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scalarMinMax32(inst, IrOpcode::UMin32, IrOpcode::ULessThan32);
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return true;
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case RdnaOpcode::SMaxU32:
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scalarMinMax32(inst, IrOpcode::UMax32, IrOpcode::UGreaterThan32);
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return true;
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case RdnaOpcode::SCmpEqU32:
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case RdnaOpcode::SCmpEqI32:
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emitIntegerCompare(inst, IrOpcode::IEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpLgU32:
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case RdnaOpcode::SCmpLgI32:
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emitIntegerCompare(inst, IrOpcode::INotEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpGtU32:
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emitIntegerCompare(inst, IrOpcode::UGreaterThan32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpGeU32:
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emitIntegerCompare(inst, IrOpcode::UGreaterThanEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpLtU32:
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emitIntegerCompare(inst, IrOpcode::ULessThan32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpLeU32:
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emitIntegerCompare(inst, IrOpcode::ULessThanEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpGtI32:
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emitIntegerCompare(inst, IrOpcode::SGreaterThan32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpGeI32:
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emitIntegerCompare(inst, IrOpcode::SGreaterThanEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpLtI32:
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emitIntegerCompare(inst, IrOpcode::SLessThan32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpLeI32:
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emitIntegerCompare(inst, IrOpcode::SLessThanEqual32, IrType::U32, true, false);
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return true;
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case RdnaOpcode::SCmpEqU64:
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emitIntegerCompare(inst, IrOpcode::IEqual64, IrType::U64, true, false);
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return true;
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case RdnaOpcode::SCmpLgU64:
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emitIntegerCompare(inst, IrOpcode::INotEqual64, IrType::U64, true, false);
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return true;
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case RdnaOpcode::SAndB64:
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return sU64Mask(inst, IrOpcode::LogicalAnd, IrOpcode::BitwiseAnd32, false, false, false);
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case RdnaOpcode::SAndn2B64:
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return sU64Mask(inst, IrOpcode::LogicalAnd, IrOpcode::BitwiseAnd32, true, false, false);
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case RdnaOpcode::SOrB64:
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return sU64Mask(inst, IrOpcode::LogicalOr, IrOpcode::BitwiseOr32, false, false, false);
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case RdnaOpcode::SOrn2B64:
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return sU64Mask(inst, IrOpcode::LogicalOr, IrOpcode::BitwiseOr32, true, false, false);
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case RdnaOpcode::SXorB64:
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return sU64Mask(inst, IrOpcode::LogicalXor, IrOpcode::BitwiseXor32, false, false, false);
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case RdnaOpcode::SNandB64:
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return sU64Mask(inst, IrOpcode::LogicalAnd, IrOpcode::BitwiseAnd32, false, true, false);
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case RdnaOpcode::SNorB64:
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return sU64Mask(inst, IrOpcode::LogicalOr, IrOpcode::BitwiseOr32, false, true, false);
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case RdnaOpcode::SXnorB64:
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return sU64Mask(inst, IrOpcode::LogicalXor, IrOpcode::BitwiseXor32, false, true, false);
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case RdnaOpcode::SNotB64:
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return sU64Mask(inst, IrOpcode::LogicalAnd, IrOpcode::BitwiseAnd32, false, false, true);
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case RdnaOpcode::SAbsI32:
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return simpleInteger(inst, IrOpcode::IAbs32, IrType::U32, false, false, true);
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case RdnaOpcode::SMulI32:
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case RdnaOpcode::SMulkI32:
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return simpleInteger(inst, IrOpcode::IMul32, IrType::U32, false, false, false);
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case RdnaOpcode::SMulHiU32:
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return simpleInteger(inst, IrOpcode::UMulHi, IrType::U32, false, false, false);
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case RdnaOpcode::SMulHiI32:
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return simpleInteger(inst, IrOpcode::SMulHi, IrType::U32, false, false, false);
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case RdnaOpcode::SAndB32:
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return simpleInteger(inst, IrOpcode::BitwiseAnd32, IrType::U32, false, false, true);
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case RdnaOpcode::SOrB32:
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return simpleInteger(inst, IrOpcode::BitwiseOr32, IrType::U32, false, false, true);
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case RdnaOpcode::SXorB32:
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return simpleInteger(inst, IrOpcode::BitwiseXor32, IrType::U32, false, false, true);
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case RdnaOpcode::SNotB32:
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return simpleInteger(inst, IrOpcode::BitwiseNot32, IrType::U32, false, false, true);
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case RdnaOpcode::SBrevB32:
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return simpleInteger(inst, IrOpcode::BitReverse32, IrType::U32, false, false, false);
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case RdnaOpcode::SBrevB64: {
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const auto source = readU32Pair(sourceAt(inst, 0u));
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const IrU32 low(ir.Emit(IrOpcode::BitReverse32, IrType::U32, {&source[1].Value()}));
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const IrU32 high(ir.Emit(IrOpcode::BitReverse32, IrType::U32, {&source[0].Value()}));
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writeU32Pair(inst.destination, {low, high});
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return true;
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}
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case RdnaOpcode::SSextI32I8:
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case RdnaOpcode::SSextI32I16: {
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const auto source = readU32(sourceAt(inst, 0u));
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const auto width = inst.op == RdnaOpcode::SSextI32I8 ? 8u : 16u;
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auto& result = ir.Emit(IrOpcode::BitFieldSExtract, IrType::U32, {&source.Value(), &ir.Constant(0u), &ir.Constant(width)});
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writeOperand(inst.destination, &result);
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return true;
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}
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case RdnaOpcode::SBcnt0I32B32:
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case RdnaOpcode::SFf0I32B32: {
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const IrU32 source = readU32(sourceAt(inst, 0u));
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auto& inverted = ir.BitwiseNot(source.Value());
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const bool count = inst.op == RdnaOpcode::SBcnt0I32B32;
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auto& result = ir.Emit(count ? IrOpcode::BitCount32 : IrOpcode::FindILsb32, IrType::U32, {&inverted});
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writeOperand(inst.destination, &result);
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if (count) {
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ir.SetScc(ir.INotEqual(result, ir.Constant(0u)));
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}
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return true;
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}
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case RdnaOpcode::SBcnt0I32B64: {
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const std::array<IrU32, 2> source = extractU64(readU64(sourceAt(inst, 0u)));
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auto& low = ir.Emit(IrOpcode::BitCount32, IrType::U32, {&ir.BitwiseNot(source[0].Value())});
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auto& high = ir.Emit(IrOpcode::BitCount32, IrType::U32, {&ir.BitwiseNot(source[1].Value())});
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auto& result = ir.IAdd(low, high);
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writeOperand(inst.destination, &result);
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ir.SetScc(ir.INotEqual(result, ir.Constant(0u)));
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return true;
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}
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case RdnaOpcode::SBcnt1I32B32:
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return simpleInteger(inst, IrOpcode::BitCount32, IrType::U32, false, false, true);
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case RdnaOpcode::SBcnt1I32B64:
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return simpleInteger(inst, IrOpcode::BitCount64, IrType::U64, false, false, true);
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case RdnaOpcode::SFf1I32B32:
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return simpleInteger(inst, IrOpcode::FindILsb32, IrType::U32, false, false, false);
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case RdnaOpcode::SLshlB32:
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return simpleInteger(inst, IrOpcode::ShiftLeftLogical32, IrType::U32, false, true, true);
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case RdnaOpcode::SLshrB32:
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return simpleInteger(inst, IrOpcode::ShiftRightLogical32, IrType::U32, false, true, true);
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case RdnaOpcode::SAshrI32:
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return simpleInteger(inst, IrOpcode::ShiftRightArithmetic32, IrType::U32, false, true, true);
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case RdnaOpcode::SAshrI64:
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return simpleInteger(inst, IrOpcode::ShiftRightArithmetic64, IrType::U64, false, false, true);
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case RdnaOpcode::SLshlB64:
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return simpleInteger(inst, IrOpcode::ShiftLeftLogical64, IrType::U64, false, false, true);
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case RdnaOpcode::SLshrB64:
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return simpleInteger(inst, IrOpcode::ShiftRightLogical64, IrType::U64, false, false, true);
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case RdnaOpcode::SAndn2B32:
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return composedIntegerBinary(inst, IrOpcode::BitwiseAnd32, true, false, true);
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case RdnaOpcode::SOrn2B32:
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return composedIntegerBinary(inst, IrOpcode::BitwiseOr32, true, false, true);
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case RdnaOpcode::SNandB32:
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return composedIntegerBinary(inst, IrOpcode::BitwiseAnd32, false, true, true);
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case RdnaOpcode::SNorB32:
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return composedIntegerBinary(inst, IrOpcode::BitwiseOr32, false, true, true);
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case RdnaOpcode::SXnorB32:
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return composedIntegerBinary(inst, IrOpcode::BitwiseXor32, false, true, true);
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case RdnaOpcode::SFf0I32B64:
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return sFfI32B64(inst, true);
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case RdnaOpcode::SFf1I32B64:
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return sFfI32B64(inst, false);
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case RdnaOpcode::SFlbitI32B32:
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return vFfbh32(inst, false);
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case RdnaOpcode::SFlbitI32:
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return vFfbh32(inst, true);
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case RdnaOpcode::SFlbitI32B64:
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return sFlbitI32B64(inst, false);
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case RdnaOpcode::SFlbitI32I64:
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return sFlbitI32B64(inst, true);
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case RdnaOpcode::SBitset0B32:
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return sBitsetB32(inst, false);
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case RdnaOpcode::SBitset1B32:
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return sBitsetB32(inst, true);
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case RdnaOpcode::SBitset0B64:
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return sBitsetB64(inst, false);
|
|
case RdnaOpcode::SBitset1B64:
|
|
return sBitsetB64(inst, true);
|
|
case RdnaOpcode::SBitreplicateB64B32:
|
|
return sBitreplicateB64B32(inst);
|
|
case RdnaOpcode::SQuadmaskB32:
|
|
return sQuadmask(inst, false);
|
|
case RdnaOpcode::SQuadmaskB64:
|
|
return sQuadmask(inst, true);
|
|
case RdnaOpcode::SMovrelsB32:
|
|
case RdnaOpcode::SMovrelsB64:
|
|
case RdnaOpcode::SMovreldB32:
|
|
case RdnaOpcode::SMovreldB64:
|
|
case RdnaOpcode::SMovrelsd2B32:
|
|
return sMovrel(inst);
|
|
case RdnaOpcode::SBfmB32:
|
|
return bfmB32(inst);
|
|
case RdnaOpcode::SBfmB64:
|
|
return sBfmB64(inst);
|
|
case RdnaOpcode::SBfeU32:
|
|
return sBfeU32(inst, false);
|
|
case RdnaOpcode::SBfeI32:
|
|
return sBfeU32(inst, true);
|
|
case RdnaOpcode::SBfeU64:
|
|
return sBfeU64(inst, false);
|
|
case RdnaOpcode::SBfeI64:
|
|
return sBfeU64(inst, true);
|
|
case RdnaOpcode::SBitcmp0B32:
|
|
return sBitcmpB32(inst, false);
|
|
case RdnaOpcode::SBitcmp1B32:
|
|
return sBitcmpB32(inst, true);
|
|
case RdnaOpcode::SBitcmp0B64:
|
|
return sBitcmpB64(inst, false);
|
|
case RdnaOpcode::SBitcmp1B64:
|
|
return sBitcmpB64(inst, true);
|
|
case RdnaOpcode::SPackLlB32B16:
|
|
return packB16(inst, false, false);
|
|
case RdnaOpcode::SPackLhB32B16:
|
|
return packB16(inst, false, true);
|
|
case RdnaOpcode::SPackHhB32B16:
|
|
return packB16(inst, true, true);
|
|
case RdnaOpcode::SNop:
|
|
case RdnaOpcode::SSleep:
|
|
case RdnaOpcode::SWakeup:
|
|
case RdnaOpcode::SSetprio:
|
|
case RdnaOpcode::STrap:
|
|
case RdnaOpcode::SClause:
|
|
case RdnaOpcode::SIcacheInv:
|
|
case RdnaOpcode::SIncperflevel:
|
|
case RdnaOpcode::SDecperflevel:
|
|
emitControlNop();
|
|
return true;
|
|
case RdnaOpcode::SRoundMode: {
|
|
const std::uint32_t initial = floatMode.has_value() ? floatMode->floatMode : 0u;
|
|
if ((inst.source0.value & 0xfu) != (initial & 0xfu)) {
|
|
throw std::runtime_error("s_round_mode " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + " changes the initial MODE rounding fields: runtime MODE changes are not implemented");
|
|
}
|
|
emitControlNop();
|
|
return true;
|
|
}
|
|
case RdnaOpcode::SDenormMode:
|
|
throw std::runtime_error("s_denorm_mode " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + ": the recompiler does not model denormal modes");
|
|
case RdnaOpcode::SSethalt:
|
|
if ((inst.source0.value & 1u) != 0u) {
|
|
throw std::runtime_error("s_sethalt " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + " halts the wave until a debugger resumes it");
|
|
}
|
|
emitControlNop();
|
|
return true;
|
|
case RdnaOpcode::SSendmsghalt:
|
|
throw std::runtime_error("s_sendmsghalt " + std::to_string(inst.source0.value) + " at pc " + std::to_string(inst.programCounter) + " halts the wave until a debugger resumes it");
|
|
case RdnaOpcode::SCodeEnd:
|
|
throw std::runtime_error("s_code_end at pc " + std::to_string(inst.programCounter) + " is reached: it marks the end of the code and raises an illegal instruction exception");
|
|
case RdnaOpcode::SRfeB64:
|
|
throw std::runtime_error("s_rfe_b64 at pc " + std::to_string(inst.programCounter) + " returns from a trap handler, and recompiled shaders run without one");
|
|
case RdnaOpcode::SWaitcntDepctr:
|
|
case RdnaOpcode::SWaitIdle:
|
|
emitWaitcnt();
|
|
return true;
|
|
case RdnaOpcode::SBarrier:
|
|
sBarrier();
|
|
return true;
|
|
case RdnaOpcode::SSendmsg:
|
|
sSendmsg(inst);
|
|
return true;
|
|
case RdnaOpcode::STtracedata:
|
|
sTtracedata();
|
|
return true;
|
|
case RdnaOpcode::SInstPrefetch:
|
|
sInstPrefetch();
|
|
return true;
|
|
case RdnaOpcode::SCbranchCdbg:
|
|
return true;
|
|
case RdnaOpcode::SBranch:
|
|
case RdnaOpcode::SCbranchScc0:
|
|
case RdnaOpcode::SCbranchScc1:
|
|
case RdnaOpcode::SCbranchVccz:
|
|
case RdnaOpcode::SCbranchVccnz:
|
|
case RdnaOpcode::SCbranchExecz:
|
|
case RdnaOpcode::SCbranchExecnz:
|
|
case RdnaOpcode::SEndpgm:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
void TranslateScalarInstruction(TranslationContext& context, const RdnaInstruction& instruction) {
|
|
throw std::runtime_error("TranslateScalarInstruction not implemented");
|
|
}
|
|
|
|
}
|