AnyPS5/core/relinker/codegen/include/codegen
ljkx 09cb86b076 feat(relinker): lower CLZERO for --to-intel
Lower CLZERO out of line instead of failing the relink: the 64-byte line
containing rAX (EAX with 67h) is cleared with four MOVNTDQ stores of
zero, the same non-temporal, weakly ordered store. The line address is
masked in xmm0 so RFLAGS stays untouched; xmm0 and rcx are spilled below
the red zone. Short sites share stubs through MatchSequence. CLZERO with
LOCK, an FS/GS override, a 66/F2/F3 prefix or longer than 15 bytes fails
the relink.

The decoder splits a REX followed by another prefix into a separate
instruction, which would hide a prefix that changes what CLZERO or the
next instruction does. The converter now fails the relink when such a
prefix-only fragment directly precedes an AMD-only instruction or would
be moved into a stub as a trailing instruction.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-01 12:30:35 +02:00
..
x86 feat(relinker): lower CLZERO for --to-intel 2026-10-01 12:30:35 +02:00
CodegenException.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
CodegenTypes.hpp feat(relinker): --to-intel lowers SSE4a sites to same-length jumps into an appended stub section 2026-09-26 19:00:39 -07:00
IAmd64OnlyConverter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionDecoder.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionRewriter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionScanner.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00