AnyPS5/core/relinker/codegen/include/codegen/x86
mugurc 92b20608e8 feat(relinker): convert for Rosetta with --to-rosetta
Rosetta runs AVX2, FMA, BMI1/2, F16C and MOVBE, but, unlike an Intel
host, it has neither RDSEED, CLWB nor RDPID. --to-rosetta converts
everything --to-intel does and lowers these three as well:

- RDSEED becomes RDRAND (the /6 form of the same opcode), which also
  returns a random value and sets CF.
- CLWB only writes a cache line back, so it becomes a NOP of the same
  length.
- RDPID becomes a load of 0 through an optional stub: Rosetta's TSC_AUX
  is a constant, not a processor index, so every thread reports
  processor 0. A site with no movable instruction after it for the jump
  is kept.

The flag implies --to-intel and conflicts with --windows. It is
independent of --macos: it only changes what the conversion produces, so
--macos alone leaves these instructions as they are, as on an Intel Mac,
and a title for Rosetta is relinked with --macos --to-rosetta. Intel
output is unchanged: the target is a parameter of the converter, Intel by
default.
2026-10-10 22:46:45 +03:00
..
Amd64OnlySubstitutionTable.hpp feat(relinker): convert for Rosetta with --to-rosetta 2026-10-10 22:46:45 +03:00
Amd64OnlySubstitutionTypes.hpp feat(relinker): convert for Rosetta with --to-rosetta 2026-10-10 22:46:45 +03:00
ClzeroLowering.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
ClzeroOperands.hpp feat(relinker): lower CLZERO for --to-intel 2026-10-01 12:30:35 +02:00
DecodedInstruction.hpp feat(relinker): convert for Rosetta with --to-rosetta 2026-10-10 22:46:45 +03:00
IAmd64OnlyInstructionMatcher.hpp feat(relinker): convert for Rosetta with --to-rosetta 2026-10-10 22:46:45 +03:00
ReciprocalLowering.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
ReciprocalOperands.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
Sha1Lowering.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
Sha1Operands.hpp feat(relinker): lower SHA-1 instructions with a memory operand 2026-10-05 02:02:13 +02:00
Sha256Lowering.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
Sha256Operands.hpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
Sse4aLowering.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
Sse4aOperands.hpp feat(relinker): --to-intel lowers SSE4a sites to same-length jumps into an appended stub section 2026-09-26 19:00:39 -07:00
StubBodyBuilder.hpp feat(relinker): relocate RIP-relative operands into --to-intel stubs 2026-10-08 11:10:38 +02:00
X64Assembler.hpp refactor(codegen): separated x86 assembler 2026-09-13 17:04:02 +03:00
X64InstructionDecoder.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
X64InstructionRewriter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
X64OpcodeConstants.hpp fix(relinker): decode XOP instructions 2026-10-10 19:27:24 +13:00
X64Register.hpp refactor(codegen): separated x86 assembler 2026-09-13 17:04:02 +03:00