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AnyPS5/core/relinker/codegen/src/x86
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Adrià Franch 5fc16a9548 feat(relinker): lower SHA-256 instructions with a memory operand 
SHA256RNDS2/MSG1/MSG2 with a memory source made `--to-intel` fail the
whole relink. The stub now spills a scratch xmm, loads the operand into
it with MOVDQU (AMD does not fault on a misaligned SHA operand, so the
unaligned load keeps that behaviour) and runs the register-form
lowering. RSP-based operands get the spill depth added to their
displacement. RIP-relative operands still fail: the stub runs at a
different address.

Co-Authored-By: Claude <noreply@anthropic.com>
 		2026-10-04 08:21:40 +02:00
..
Amd64OnlyInstructionMatcher.cpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
ClzeroLowering.cpp feat(relinker): lower CLZERO for --to-intel 2026-10-01 12:30:35 +02:00
ClzeroOperands.cpp fix(relinker): ignore a REX prefix that is followed by another prefix 2026-10-01 13:09:11 +02:00
DecodedInstruction.cpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
ReciprocalLowering.cpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
ReciprocalOperands.cpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
Sha1Lowering.cpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
Sha1Operands.cpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
Sha256Lowering.cpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
Sha256Operands.cpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
Sse4aLowering.cpp fix(relinker): zero dst[127:64] in EXTRQ and INSERTQ lowerings 2026-10-03 08:21:33 +02:00
Sse4aOperands.cpp fix(relinker): ignore a REX prefix that is followed by another prefix 2026-10-01 13:09:11 +02:00
StubBodyBuilder.cpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
X64InstructionDecoder.cpp fix(relinker): report RIP-relative operands of VEX, EVEX and 0F38/0F3A instructions 2026-10-03 08:10:29 +02:00
X64InstructionRewriter.cpp fix(relinker): ignore a REX prefix that is followed by another prefix 2026-10-01 13:09:11 +02:00