Adrià Franch 5fc16a9548 feat(relinker): lower SHA-256 instructions with a memory operand ... SHA256RNDS2/MSG1/MSG2 with a memory source made `--to-intel` fail the whole relink. The stub now spills a scratch xmm, loads the operand into it with MOVDQU (AMD does not fault on a misaligned SHA operand, so the unaligned load keeps that behaviour) and runs the register-form lowering. RSP-based operands get the spill depth added to their displacement. RIP-relative operands still fail: the stub runs at a different address. Co-Authored-By: Claude <noreply@anthropic.com>		2026-10-04 08:21:40 +02:00
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x86	feat(relinker): lower SHA-256 instructions with a memory operand	2026-10-04 08:21:40 +02:00
Amd64OnlyConverter.cpp	fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel	2026-10-04 14:40:16 +13:00
InstructionScanner.cpp	style: drop the branch's code comments per CONVENTIONS.md	2026-09-29 21:25:29 +03:00