shader: allow RDNA2 SDWA partial destinations for i24 multiply
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nmzik
parent
5c83060481
commit
1d41ddb378
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@ -35,7 +35,7 @@ constexpr Vop2OpcodeInfo VOP2_OPCODE_LIST[] = {
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{0x04u, Opcode::V_SUB_F32, Vop2SdwaProfile::Float32},
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{0x05u, Opcode::V_SUBREV_F32},
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{0x08u, Opcode::V_MUL_F32, Vop2SdwaProfile::Float32},
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{0x09u, Opcode::V_MUL_I32_I24, Vop2SdwaProfile::IntegerFullDestination},
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{0x09u, Opcode::V_MUL_I32_I24, Vop2SdwaProfile::IntegerPartialDestination},
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{0x0bu, Opcode::V_MUL_U32_U24, Vop2SdwaProfile::IntegerFullDestination},
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{0x0fu, Opcode::V_MIN_F32},
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{0x10u, Opcode::V_MAX_F32},
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@ -21531,6 +21531,65 @@ TestCase Vop2SdwaMaxI32CapturedHighWord(u32 wave_size) {
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return test;
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}
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TestCase Vop2SdwaMulI24Destinations(u32 wave_size) {
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using O = ShaderOpcode;
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constexpr std::array<u32, 5> sources{
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0xdead1234u, 0xabcdffffu, 0x98768001u, 0x34560000u, 0x56789abcu};
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constexpr std::array<u32, 10> captured_expected{
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0xdead91a0u, 0xdead3400u, 0xabcdfff8u, 0xabcdff00u,
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0x98760008u, 0x98760100u, 0x34560000u, 0x34560000u,
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0x56789abcu, 0x56789abcu};
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constexpr std::array<u32, 18> partial_expected{
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0x00000080u, 0xffffff80u, 0xa1b2c380u,
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0x00008000u, 0xffff8000u, 0xa1b280d4u,
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0x00800000u, 0xff800000u, 0xa180c3d4u,
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0x80000000u, 0x80000000u, 0x80b2c3d4u,
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0x0000a180u, 0xffffa180u, 0xa1b2a180u,
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0xa1800000u, 0xa1800000u, 0xa180c3d4u};
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TestCase test;
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test.name = wave_size == 64 ? "Vop2SdwaMulI24DestinationsWave64"
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: "Vop2SdwaMulI24DestinationsWave32";
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test.initial.assign(sources.begin(), sources.end());
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test.initial.push_back(0xabcde080u);
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test.expected = test.initial;
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auto &code = test.code;
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for (u32 index = 0; index < sources.size(); ++index) {
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AppendVMovU32(&code, 30, index * sizeof(u32));
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AppendBufferLoadDword(&code, 12, 30);
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AppendBufferLoadDword(&code, 26, 30);
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AppendSMovLiteral(&code, 106, 256);
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code.push_back(EncodeSMovB32(126, InlineU32(index + 1u == sources.size() ? 0 : 1)));
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// Captured WORD0/PRESERVE encodings alias their source and destination.
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code.insert(code.end(), {0x121818f9u, 0x04861488u,
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0x123434f9u, 0x0486146au});
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code.push_back(EncodeSMovB32(126, InlineU32(1)));
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AppendStoreVgpr(&code, 12, static_cast<u32>(test.expected.size()));
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AppendStoreVgpr(&code, 26, static_cast<u32>(test.expected.size()) + 1u);
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test.expected.push_back(captured_expected[index * 2u]);
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test.expected.push_back(captured_expected[index * 2u + 1u]);
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}
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AppendVMovU32(&code, 30, sources.size() * sizeof(u32));
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AppendBufferLoadDword(&code, 12, 30);
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for (u32 selector = 0; selector < 6; ++selector) {
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for (u32 unused = 0; unused < 3; ++unused) {
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AppendVMovLiteral(&code, 26, 0xa1b2c3d4u);
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code.push_back(EncodeVop2(0x09, 26, 249, 12));
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code.push_back(EncodeVop2Sdwa(InlineU32(3), selector, unused, 6, 4,
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0, 0, 0, 0, 0, 0, 1));
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AppendStoreVgpr(&code, 26, static_cast<u32>(test.expected.size()));
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test.expected.push_back(partial_expected[selector * 3u + unused]);
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}
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}
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AppendEnd(&code);
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test.initial.resize(test.expected.size());
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test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::BUFFER_LOAD_DWORD,
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O::V_MUL_I32_I24, O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpIMul", "OpBitFieldUExtract"};
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test.compute_info.wave_size = wave_size;
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test.has_compute_info = true;
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return test;
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}
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TestCase Vop2SdwaLshrrevCapturedByte1Source() {
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using O = ShaderOpcode;
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@ -34595,6 +34654,8 @@ std::vector<TestCase> MakeCases() {
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AddCase(Vop2SdwaAshrrevCapturedWord0SignExtends);
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cases.push_back(Vop2SdwaMaxI32CapturedHighWord(32));
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cases.push_back(Vop2SdwaMaxI32CapturedHighWord(64));
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cases.push_back(Vop2SdwaMulI24Destinations(32));
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cases.push_back(Vop2SdwaMulI24Destinations(64));
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AddCase(Vop2SdwaLshrrevCapturedByte1Source);
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AddCase(Vop2SdwaSubNcPreservesByteAndWordDestinations);
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AddCase(Vop3CvtPkI16I32Captured);
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@ -40415,6 +40476,13 @@ int main(int argc, char **argv) {
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RunCase(&vulkan, VectorAddcWritesPerLaneCarryOut());
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return 0;
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}
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if (argc == 2 && std::strcmp(argv[1], "--sdwa-mul-i24-only") == 0) {
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VulkanHarness vulkan;
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RunCase(&vulkan, Vop2SdwaMulI24Destinations(32));
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RunCase(&vulkan, Vop2SdwaMulI24Destinations(64));
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RunCase(&vulkan, VectorIntegerOps());
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return 0;
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}
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if (argc == 2 && std::strcmp(argv[1], "--cvt-pk-i16-only") == 0) {
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VulkanHarness vulkan;
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RunCase(&vulkan, Vop3CvtPkI16I32Captured());
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@ -3668,6 +3668,39 @@ void TestNewShaderRecompilerVop1SdwaBfrev() {
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}
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}
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void TestVop2SdwaMulI24Destination() {
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using namespace ShaderRecompiler::Decoder;
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const uint32_t captured[][2] = {
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{0x121818f9u, 0x04861488u}, {0x123434f9u, 0x0486146au}};
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for (uint32_t index = 0; index < 2; ++index) {
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Instruction decoded;
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DecodeInstruction(captured[index], 0, decoded);
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const uint32_t reg = index == 0 ? 12u : 26u;
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Check(decoded.opcode == Opcode::V_MUL_I32_I24 && decoded.word_count == 2 &&
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decoded.dst.kind == OperandKind::Vgpr && decoded.dst.reg == reg &&
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decoded.dst.sdwa_sel == 4 && decoded.dst.sdwa_dst_unused == 2 &&
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decoded.dst.explicit_sdwa_dst && !decoded.dst.clamp &&
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decoded.dst.omod == 0 && decoded.src0.sdwa_sel == 6 &&
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decoded.src1.kind == OperandKind::Vgpr && decoded.src1.reg == reg &&
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decoded.src1.sdwa_sel == 4 && !decoded.src1.sdwa_sext,
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"captured V_MUL_I32_I24 SDWA destination/source metadata is incorrect");
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Check(index == 0 ? decoded.src0.kind == OperandKind::IntegerInlineConstant &&
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decoded.src0.value == 8
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: decoded.src0.kind == OperandKind::VccLo,
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"captured V_MUL_I32_I24 SDWA scalar source is incorrect");
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}
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for (const uint32_t modifier : {
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0x04861788u, 0x04861c88u, 0x04871488u, 0x07861488u,
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0x04961488u, 0x04a61488u, 0x14861488u, 0x24861488u,
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0x04863488u, 0x04865488u}) {
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const uint32_t invalid[] = {captured[0][0], modifier};
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Instruction decoded;
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DecodeInstruction(invalid, 0, decoded);
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Check(decoded.opcode == Opcode::UNSUPPORTED && decoded.word_count == 2,
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"V_MUL_I32_I24 SDWA accepted reserved selectors or float modifiers");
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}
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}
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void TestNewShaderRecompilerVop1SdwaNotDestination() {
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auto options = MakeCompileOptions(ShaderType::Pixel);
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@ -14784,6 +14817,7 @@ int main() {
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TestNewShaderRecompilerF64AluEncodings();
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TestNewShaderRecompilerVop1SdwaBfrev();
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TestNewShaderRecompilerVop1SdwaNotDestination();
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TestVop2SdwaMulI24Destination();
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TestNewShaderRecompilerScalarMemoryBindingDomains();
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// Opcode semantics and optimized SPIR-V are exercised by
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// ShaderRecompilerComputeTests; keep the distinct decoder contract checks
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