shader: add missing 64-bit integer image atomics
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
This commit is contained in:
nmzik
parent
de9c15fa79
commit
af3011cd69
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@ -321,15 +321,21 @@ inline constexpr auto EmitImageSampleRaw = EmitImage;
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inline constexpr auto EmitImageGatherRaw = EmitImage;
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inline constexpr auto EmitImageAtomicCompareSwap32 = EmitImage;
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inline constexpr auto EmitImageAtomicSwap32 = EmitImage;
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inline constexpr auto EmitImageAtomicSwap64 = EmitImage;
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inline constexpr auto EmitImageAtomicIAdd32 = EmitImage;
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inline constexpr auto EmitImageAtomicIAdd64 = EmitImage;
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inline constexpr auto EmitImageAtomicSMin32 = EmitImage;
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inline constexpr auto EmitImageAtomicUMin32 = EmitImage;
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inline constexpr auto EmitImageAtomicUMin64 = EmitImage;
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inline constexpr auto EmitImageAtomicSMax32 = EmitImage;
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inline constexpr auto EmitImageAtomicUMax32 = EmitImage;
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inline constexpr auto EmitImageAtomicUMax64 = EmitImage;
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inline constexpr auto EmitImageAtomicAnd32 = EmitImage;
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inline constexpr auto EmitImageAtomicAnd64 = EmitImage;
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inline constexpr auto EmitImageAtomicOr32 = EmitImage;
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inline constexpr auto EmitImageAtomicOr64 = EmitImage;
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inline constexpr auto EmitImageAtomicXor32 = EmitImage;
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inline constexpr auto EmitImageAtomicXor64 = EmitImage;
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inline constexpr auto EmitImageAtomicFMin32 = EmitImage;
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inline constexpr auto EmitImageAtomicFMax32 = EmitImage;
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void EmitUnreachable(ValueEmitContext& ctx, const IR::Inst& inst);
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@ -361,10 +361,12 @@ spv::Op SpirvAtomicOpcode(IR::ValueOpcode opcode) {
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case IR::ValueOpcode::ImageAtomicCompareSwap32:
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case IR::ValueOpcode::BufferAtomicCmpSwap32: return spv::OpAtomicCompareExchange;
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case IR::ValueOpcode::ImageAtomicSwap32:
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case IR::ValueOpcode::ImageAtomicSwap64:
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case IR::ValueOpcode::BufferAtomicSwap32:
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case IR::ValueOpcode::BufferAtomicSwap64:
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case IR::ValueOpcode::SharedAtomicSwap32: return spv::OpAtomicExchange;
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case IR::ValueOpcode::ImageAtomicIAdd32:
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case IR::ValueOpcode::ImageAtomicIAdd64:
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case IR::ValueOpcode::BufferAtomicIAdd32:
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case IR::ValueOpcode::SharedAtomicIAdd64:
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case IR::ValueOpcode::SharedAtomicIAdd32: return spv::OpAtomicIAdd;
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@ -374,6 +376,7 @@ spv::Op SpirvAtomicOpcode(IR::ValueOpcode opcode) {
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case IR::ValueOpcode::BufferAtomicSMin32:
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case IR::ValueOpcode::SharedAtomicSMin32: return spv::OpAtomicSMin;
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case IR::ValueOpcode::ImageAtomicUMin32:
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case IR::ValueOpcode::ImageAtomicUMin64:
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case IR::ValueOpcode::BufferAtomicUMin32:
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case IR::ValueOpcode::SharedAtomicUMin32: return spv::OpAtomicUMin;
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case IR::ValueOpcode::ImageAtomicSMax32:
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@ -384,15 +387,18 @@ spv::Op SpirvAtomicOpcode(IR::ValueOpcode opcode) {
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case IR::ValueOpcode::BufferAtomicUMax32:
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case IR::ValueOpcode::SharedAtomicUMax32: return spv::OpAtomicUMax;
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case IR::ValueOpcode::ImageAtomicAnd32:
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case IR::ValueOpcode::ImageAtomicAnd64:
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case IR::ValueOpcode::BufferAtomicAnd32:
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case IR::ValueOpcode::BufferAtomicAnd64:
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case IR::ValueOpcode::SharedAtomicAnd32: return spv::OpAtomicAnd;
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case IR::ValueOpcode::ImageAtomicOr32:
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case IR::ValueOpcode::ImageAtomicOr64:
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case IR::ValueOpcode::BufferAtomicOr32:
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case IR::ValueOpcode::BufferAtomicOr64:
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case IR::ValueOpcode::SharedAtomicOr64:
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case IR::ValueOpcode::SharedAtomicOr32: return spv::OpAtomicOr;
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case IR::ValueOpcode::ImageAtomicXor32:
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case IR::ValueOpcode::ImageAtomicXor64:
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case IR::ValueOpcode::BufferAtomicXor32:
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case IR::ValueOpcode::SharedAtomicXor32: return spv::OpAtomicXor;
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default: return spv::OpNop;
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@ -20,6 +20,12 @@ struct MimgGatherInfo {
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uint32_t flags = 0;
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};
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struct MimgAtomicInfo {
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uint32_t encoding = 0;
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Opcode decoded = Opcode::UNSUPPORTED;
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bool supports_64 = false;
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};
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constexpr ImageDimension DecodeImageDimension(uint32_t dim) {
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switch (dim) {
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case 0u: return ImageDimension::Dim1D;
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@ -190,17 +196,17 @@ constexpr MimgGatherInfo MIMG_GATHER_OPCODE_LIST[] = {
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{0x61u, Opcode::IMAGE_GATHER4H, ImageSampleFlagGatherHorizontal},
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};
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constexpr Detail::OpcodeMap MIMG_ATOMIC_OPCODE_LIST[] = {
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{0x0fu, Opcode::IMAGE_ATOMIC_SWAP},
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constexpr MimgAtomicInfo MIMG_ATOMIC_OPCODE_LIST[] = {
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{0x0fu, Opcode::IMAGE_ATOMIC_SWAP, true},
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{0x10u, Opcode::IMAGE_ATOMIC_CMPSWAP},
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{0x11u, Opcode::IMAGE_ATOMIC_ADD},
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{0x11u, Opcode::IMAGE_ATOMIC_ADD, true},
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{0x14u, Opcode::IMAGE_ATOMIC_SMIN},
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{0x15u, Opcode::IMAGE_ATOMIC_UMIN},
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{0x15u, Opcode::IMAGE_ATOMIC_UMIN, true},
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{0x16u, Opcode::IMAGE_ATOMIC_SMAX},
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{0x17u, Opcode::IMAGE_ATOMIC_UMAX},
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{0x18u, Opcode::IMAGE_ATOMIC_AND},
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{0x19u, Opcode::IMAGE_ATOMIC_OR},
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{0x1au, Opcode::IMAGE_ATOMIC_XOR},
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{0x17u, Opcode::IMAGE_ATOMIC_UMAX, true},
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{0x18u, Opcode::IMAGE_ATOMIC_AND, true},
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{0x19u, Opcode::IMAGE_ATOMIC_OR, true},
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{0x1au, Opcode::IMAGE_ATOMIC_XOR, true},
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{0x1eu, Opcode::IMAGE_ATOMIC_FMIN},
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{0x1fu, Opcode::IMAGE_ATOMIC_FMAX},
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};
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@ -210,7 +216,7 @@ constexpr auto MIMG_GATHER_OPS = Detail::MakeOpcodeTable<0x100>(MIMG_GATHER_OPCO
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constexpr auto MIMG_ATOMIC_OPS = Detail::MakeOpcodeTable<0x100>(MIMG_ATOMIC_OPCODE_LIST);
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Opcode DecodeMimgOpcode(uint32_t opcode, const MimgSampleInfo* sample, const MimgGatherInfo* gather,
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const Detail::OpcodeMap* atomic) {
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const MimgAtomicInfo* atomic) {
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if (sample != nullptr) {
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return Opcode::IMAGE_SAMPLE;
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}
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@ -246,7 +252,7 @@ uint32_t DecodeMimgSampleFlags(const MimgSampleInfo* sample, const MimgGatherInf
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uint32_t DecodeMimgAddressComponents(uint32_t opcode, ImageDimension dimension,
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const MimgSampleInfo* sample, const MimgGatherInfo* gather,
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const Detail::OpcodeMap* atomic) {
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const MimgAtomicInfo* atomic) {
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if (sample != nullptr) {
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return ImageSampleAddressComponents(sample->flags, dimension);
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}
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@ -370,7 +376,7 @@ void DecodeMimg(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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SetUnsupported(inst, Family::MIMG, opcode, "MIMG image atomic has invalid DMASK");
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} else if (inst.dmask == mask64) {
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inst.data_bits = 64u;
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if (inst.opcode != Opcode::IMAGE_ATOMIC_UMAX) {
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if (!atomic->supports_64) {
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SetUnsupported(inst, Family::MIMG, opcode,
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"MIMG 64-bit image atomic opcode is not implemented");
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}
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@ -546,7 +546,10 @@ void Translator::BUFFER_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode
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}
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}
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void Translator::IMAGE_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode) {
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void Translator::IMAGE_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode32,
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IR::ValueOpcode opcode64) {
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const auto opcode = inst.data_bits == 64u ? opcode64 : opcode32;
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EXIT_IF(opcode == IR::ValueOpcode::Count);
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const auto memory = MemoryInfoFromDecoded(inst);
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const auto resource = GetImageResource(memory);
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const auto address = MakeImageAddress(inst, MemorySourceAt(inst, 1));
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@ -1041,24 +1044,30 @@ void Translator::EmitMemory(const Decoder::Instruction& inst) {
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case Decoder::Opcode::IMAGE_ATOMIC_CMPSWAP:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicCompareSwap32);
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case Decoder::Opcode::IMAGE_ATOMIC_SWAP:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicSwap32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicSwap32,
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IR::ValueOpcode::ImageAtomicSwap64);
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case Decoder::Opcode::IMAGE_ATOMIC_ADD:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicIAdd32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicIAdd32,
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IR::ValueOpcode::ImageAtomicIAdd64);
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case Decoder::Opcode::IMAGE_ATOMIC_SMIN:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicSMin32);
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case Decoder::Opcode::IMAGE_ATOMIC_UMIN:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicUMin32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicUMin32,
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IR::ValueOpcode::ImageAtomicUMin64);
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case Decoder::Opcode::IMAGE_ATOMIC_SMAX:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicSMax32);
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case Decoder::Opcode::IMAGE_ATOMIC_UMAX:
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return IMAGE_ATOMIC(inst, inst.data_bits == 64u ? IR::ValueOpcode::ImageAtomicUMax64
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: IR::ValueOpcode::ImageAtomicUMax32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicUMax32,
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IR::ValueOpcode::ImageAtomicUMax64);
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case Decoder::Opcode::IMAGE_ATOMIC_AND:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicAnd32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicAnd32,
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IR::ValueOpcode::ImageAtomicAnd64);
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case Decoder::Opcode::IMAGE_ATOMIC_OR:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicOr32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicOr32,
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IR::ValueOpcode::ImageAtomicOr64);
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case Decoder::Opcode::IMAGE_ATOMIC_XOR:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicXor32);
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicXor32,
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IR::ValueOpcode::ImageAtomicXor64);
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case Decoder::Opcode::IMAGE_ATOMIC_FMIN:
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return IMAGE_ATOMIC(inst, IR::ValueOpcode::ImageAtomicFMin32);
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case Decoder::Opcode::IMAGE_ATOMIC_FMAX:
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@ -86,7 +86,8 @@ private:
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void BUFFER_LOAD(const Decoder::Instruction& inst);
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void BUFFER_STORE(const Decoder::Instruction& inst);
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void BUFFER_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode);
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void IMAGE_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode);
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void IMAGE_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode32,
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IR::ValueOpcode opcode64 = IR::ValueOpcode::Count);
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void DS_ATOMIC(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool returns_value);
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void FLAT_LOAD(const Decoder::Instruction& inst);
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void FLAT_STORE(const Decoder::Instruction& inst);
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@ -224,15 +224,21 @@ ImageOpcodeInfo ImageOpcodeInfoOf(ValueOpcode opcode) {
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return {ImageAccess::Write, ImageResourceClass::Storage, false};
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case ValueOpcode::ImageAtomicCompareSwap32:
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case ValueOpcode::ImageAtomicSwap32:
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case ValueOpcode::ImageAtomicSwap64:
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case ValueOpcode::ImageAtomicIAdd32:
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case ValueOpcode::ImageAtomicIAdd64:
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case ValueOpcode::ImageAtomicSMin32:
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case ValueOpcode::ImageAtomicUMin32:
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case ValueOpcode::ImageAtomicUMin64:
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case ValueOpcode::ImageAtomicSMax32:
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case ValueOpcode::ImageAtomicUMax32:
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case ValueOpcode::ImageAtomicUMax64:
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case ValueOpcode::ImageAtomicAnd32:
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case ValueOpcode::ImageAtomicAnd64:
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case ValueOpcode::ImageAtomicOr32:
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case ValueOpcode::ImageAtomicOr64:
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case ValueOpcode::ImageAtomicXor32:
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case ValueOpcode::ImageAtomicXor64:
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case ValueOpcode::ImageAtomicFMin32:
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case ValueOpcode::ImageAtomicFMax32:
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return {ImageAccess::Atomic, ImageResourceClass::Storage, false};
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@ -310,15 +310,21 @@ VALUE_OPCODE(ImageSampleRaw, U32x4, ImageResource, SamplerResource, ImageAddress
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VALUE_OPCODE(ImageGatherRaw, U32x4, ImageResource, SamplerResource, ImageAddress, U32, U32, U32, U32)
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VALUE_OPCODE(ImageAtomicCompareSwap32, U32, ImageResource, ImageAddress, U32, U32, U1)
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VALUE_OPCODE(ImageAtomicSwap32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicSwap64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicIAdd32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicIAdd64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicSMin32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicUMin32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicUMin64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicSMax32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicUMax32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicUMax64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicAnd32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicAnd64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicOr32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicOr64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicXor32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicXor64, U64, ImageResource, ImageAddress, U64, U1)
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VALUE_OPCODE(ImageAtomicFMin32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(ImageAtomicFMax32, U32, ImageResource, ImageAddress, U32, U1)
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VALUE_OPCODE(GetAttribute, U32, U32, U32)
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@ -33646,20 +33646,68 @@ TestCase ImageAtomicVariants() {
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return test;
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}
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template <bool wide> TestCase ImageAtomicUMaxGlcAndExec() {
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// Input and old texel: high DWORD ordering, unsigned sign boundary, and
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// equal-high-DWORD ordering must all survive the RG32_UINT -> R64_UINT view.
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constexpr uint64_t values[][2] = {
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{0x0000000100000001ull, 0x00000000ffffffffull},
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{0x00000000ffffffffull, 0x0000000100000001ull},
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{0x8000000000000000ull, 0x7fffffffffffffffull},
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{0x12345678ffffffffull, 0x1234567800000001ull},
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{0xffffffffffffffffull, 0x8000000000000000ull},
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};
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constexpr u32 texel_dwords = wide ? 2 : 1;
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// Input and old texel cover high-DWORD ordering, carry/wrap, the unsigned sign
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// boundary, and equal-high-DWORD ordering through the RG32_UINT -> R64_UINT view.
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constexpr uint64_t ImageAtomicInputs[][2] = {
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{0x0000000100000001ull, 0x00000000ffffffffull},
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{0x00000000ffffffffull, 0x0000000100000001ull},
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{0x8000000000000000ull, 0x7fffffffffffffffull},
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{0x12345678ffffffffull, 0x1234567800000001ull},
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{0xffffffffffffffffull, 0x8000000000000000ull},
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};
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struct ImageAtomicIntegerCase {
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u32 encoding;
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ShaderOpcode opcode;
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const char *name32;
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const char *name64;
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const char *spirv;
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uint64_t expected64[std::size(ImageAtomicInputs)];
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u32 expected32[std::size(ImageAtomicInputs)];
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};
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constexpr ImageAtomicIntegerCase ImageAtomicIntegerCases[] = {
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{0x0fu, ShaderOpcode::IMAGE_ATOMIC_SWAP,
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"ImageAtomicSwap32GlcAndExec", "ImageAtomicSwap64GlcAndExec", "OpAtomicExchange",
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{0x0000000100000001ull, 0x00000000ffffffffull, 0x8000000000000000ull,
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0x12345678ffffffffull, 0xffffffffffffffffull},
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{0x00000001u, 0xffffffffu, 0x00000000u, 0xffffffffu, 0xffffffffu}},
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{0x11u, ShaderOpcode::IMAGE_ATOMIC_ADD,
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"ImageAtomicAdd32GlcAndExec", "ImageAtomicAdd64GlcAndExec", "OpAtomicIAdd",
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{0x0000000200000000ull, 0x0000000200000000ull, 0xffffffffffffffffull,
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0x2468acf100000000ull, 0x7fffffffffffffffull},
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{0x00000000u, 0x00000000u, 0xffffffffu, 0x00000000u, 0xffffffffu}},
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{0x15u, ShaderOpcode::IMAGE_ATOMIC_UMIN,
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"ImageAtomicUMin32GlcAndExec", "ImageAtomicUMin64GlcAndExec", "OpAtomicUMin",
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{0x00000000ffffffffull, 0x00000000ffffffffull, 0x7fffffffffffffffull,
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0x1234567800000001ull, 0x8000000000000000ull},
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{0x00000001u, 0x00000001u, 0x00000000u, 0x00000001u, 0x00000000u}},
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{0x17u, ShaderOpcode::IMAGE_ATOMIC_UMAX,
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"ImageAtomicUMax32GlcAndExec", "ImageAtomicUMax64GlcAndExec", "OpAtomicUMax",
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{0x0000000100000001ull, 0x0000000100000001ull, 0x8000000000000000ull,
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0x12345678ffffffffull, 0xffffffffffffffffull},
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{0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu}},
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{0x18u, ShaderOpcode::IMAGE_ATOMIC_AND,
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"ImageAtomicAnd32GlcAndExec", "ImageAtomicAnd64GlcAndExec", "OpAtomicAnd",
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{0x0000000000000001ull, 0x0000000000000001ull, 0x0000000000000000ull,
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0x1234567800000001ull, 0x8000000000000000ull},
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{0x00000001u, 0x00000001u, 0x00000000u, 0x00000001u, 0x00000000u}},
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{0x19u, ShaderOpcode::IMAGE_ATOMIC_OR,
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"ImageAtomicOr32GlcAndExec", "ImageAtomicOr64GlcAndExec", "OpAtomicOr",
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{0x00000001ffffffffull, 0x00000001ffffffffull, 0xffffffffffffffffull,
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0x12345678ffffffffull, 0xffffffffffffffffull},
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{0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu}},
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{0x1au, ShaderOpcode::IMAGE_ATOMIC_XOR,
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"ImageAtomicXor32GlcAndExec", "ImageAtomicXor64GlcAndExec", "OpAtomicXor",
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{0x00000001fffffffeull, 0x00000001fffffffeull, 0xffffffffffffffffull,
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0x00000000fffffffeull, 0x7fffffffffffffffull},
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{0xfffffffeu, 0xfffffffeu, 0xffffffffu, 0xfffffffeu, 0xffffffffu}},
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};
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TestCase ImageAtomicIntegerGlcAndExec(const ImageAtomicIntegerCase &atomic, bool wide) {
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const u32 texel_dwords = wide ? 2 : 1;
|
||||
TestCase test;
|
||||
test.name = wide ? "ImageAtomicUMax64CapturedGlcAndExec"
|
||||
: "ImageAtomicUMax32GlcAndExec";
|
||||
test.name = wide ? atomic.name64 : atomic.name32;
|
||||
test.user_data = MakeStorageTextureData(wide ? Prospero::BufferFormat::k32_32UInt
|
||||
: Prospero::BufferFormat::k32UInt);
|
||||
test.has_user_data = true;
|
||||
|
|
@ -33667,25 +33715,21 @@ template <bool wide> TestCase ImageAtomicUMaxGlcAndExec() {
|
|||
test.expected_storage_image_r32ui = test.storage_image_r32ui;
|
||||
auto &code = test.code;
|
||||
code.push_back(EncodeSop1(0x04, 12, 126)); // Preserve EXEC.
|
||||
for (u32 i = 0; i < std::size(values); ++i) {
|
||||
const auto input = values[i][0];
|
||||
const auto old = values[i][1];
|
||||
for (u32 i = 0; i < std::size(ImageAtomicInputs); ++i) {
|
||||
const auto input = ImageAtomicInputs[i][0];
|
||||
const auto old = ImageAtomicInputs[i][1];
|
||||
const bool glc = i != 0 && i != 4;
|
||||
AppendVMovU32(&code, 0, i & 3u);
|
||||
AppendVMovU32(&code, 1, i >> 2u);
|
||||
AppendVMovLiteral(&code, 2, static_cast<u32>(input));
|
||||
AppendVMovLiteral(&code, 3, static_cast<u32>(input >> 32u));
|
||||
// Captured PS5 instruction: f05c0308 00000200, DMASK=3, VDATA=v[2:3].
|
||||
code.insert(code.end(), {0xf05c0108u | (wide ? 0x200u : 0u) |
|
||||
(glc ? 0x2000u : 0u),
|
||||
0x00000200u});
|
||||
code.push_back(EncodeMimg0(atomic.encoding, wide ? 3u : 1u, 0, glc));
|
||||
code.push_back(EncodeMimg1(2, 0));
|
||||
AppendStoreVgpr(&code, 2, i * 2);
|
||||
AppendStoreVgpr(&code, 3, i * 2 + 1);
|
||||
test.expected.push_back(static_cast<u32>(glc ? old : input));
|
||||
test.expected.push_back(static_cast<u32>((wide && glc ? old : input) >> 32u));
|
||||
const uint64_t result = wide ? std::max(input, old)
|
||||
: std::max(static_cast<u32>(input),
|
||||
static_cast<u32>(old));
|
||||
const uint64_t result = wide ? atomic.expected64[i] : atomic.expected32[i];
|
||||
for (u32 word = 0; word < texel_dwords; ++word) {
|
||||
test.storage_image_r32ui[i * texel_dwords + word] =
|
||||
static_cast<u32>(old >> (word * 32u));
|
||||
|
|
@ -33693,23 +33737,30 @@ template <bool wide> TestCase ImageAtomicUMaxGlcAndExec() {
|
|||
static_cast<u32>(result >> (word * 32u));
|
||||
}
|
||||
}
|
||||
// A leaked update must change the inactive texel for every operation.
|
||||
const bool clear_bits = atomic.opcode == ShaderOpcode::IMAGE_ATOMIC_AND ||
|
||||
atomic.opcode == ShaderOpcode::IMAGE_ATOMIC_UMIN;
|
||||
const u32 inactive = clear_bits ? 0xffffffffu : 0u;
|
||||
for (u32 word = 0; word < texel_dwords; ++word) {
|
||||
test.storage_image_r32ui[5u * texel_dwords + word] = inactive;
|
||||
test.expected_storage_image_r32ui[5u * texel_dwords + word] = inactive;
|
||||
}
|
||||
AppendVMovU32(&code, 0, 1);
|
||||
AppendVMovU32(&code, 1, 1); // Untouched zero texel, so an EXEC leak is observable.
|
||||
AppendVMovU32(&code, 1, 1);
|
||||
AppendVMovLiteral(&code, 2, 0xabcdef01u);
|
||||
AppendVMovLiteral(&code, 3, 0x87654321u);
|
||||
code.push_back(EncodeSop1(0x04, 126, InlineU32(0)));
|
||||
code.insert(code.end(), {0xf05c2108u | (wide ? 0x200u : 0u), 0x00000200u});
|
||||
code.push_back(EncodeMimg0(atomic.encoding, wide ? 3u : 1u, 0, true));
|
||||
code.push_back(EncodeMimg1(2, 0));
|
||||
code.push_back(EncodeSop1(0x04, 126, 12));
|
||||
AppendStoreVgpr(&code, 2, std::size(values) * 2);
|
||||
AppendStoreVgpr(&code, 3, std::size(values) * 2 + 1);
|
||||
AppendStoreVgpr(&code, 2, std::size(ImageAtomicInputs) * 2);
|
||||
AppendStoreVgpr(&code, 3, std::size(ImageAtomicInputs) * 2 + 1);
|
||||
test.expected.insert(test.expected.end(), {0xabcdef01u, 0x87654321u});
|
||||
AppendEnd(&code);
|
||||
test.opcodes = {ShaderOpcode::V_MOV_B32, ShaderOpcode::S_MOV_B64,
|
||||
ShaderOpcode::IMAGE_ATOMIC_UMAX, ShaderOpcode::BUFFER_STORE_DWORD,
|
||||
ShaderOpcode::S_ENDPGM};
|
||||
test.required_spirv = {"OpAtomicUMax", "OpImageTexelPointer",
|
||||
wide ? "R64ui" : "R32ui"};
|
||||
if constexpr (wide) {
|
||||
atomic.opcode, ShaderOpcode::BUFFER_STORE_DWORD, ShaderOpcode::S_ENDPGM};
|
||||
test.required_spirv = {atomic.spirv, "OpImageTexelPointer", wide ? "R64ui" : "R32ui"};
|
||||
if (wide) {
|
||||
test.required_spirv.push_back("Int64ImageEXT");
|
||||
test.required_spirv.push_back("SPV_EXT_shader_image_int64");
|
||||
}
|
||||
|
|
@ -34802,8 +34853,10 @@ std::vector<TestCase> MakeCases() {
|
|||
AddCase(ImageAtomicSwapReturnsPreviousTexel);
|
||||
AddCase(ImageStoreAndAtomicUseSeparateBindings);
|
||||
AddCase(ImageAtomicVariants);
|
||||
AddCase(ImageAtomicUMaxGlcAndExec<false>);
|
||||
AddCase(ImageAtomicUMaxGlcAndExec<true>);
|
||||
for (const auto &atomic : ImageAtomicIntegerCases) {
|
||||
cases.push_back(ImageAtomicIntegerGlcAndExec(atomic, false));
|
||||
cases.push_back(ImageAtomicIntegerGlcAndExec(atomic, true));
|
||||
}
|
||||
AddCase(ImageAtomicFloatGlcAndExec<true>);
|
||||
AddCase(ImageAtomicFloatGlcAndExec<false>);
|
||||
AddCase(ImageAtomicFloatSpecialValues<true>);
|
||||
|
|
@ -40121,8 +40174,10 @@ int main(int argc, char **argv) {
|
|||
}
|
||||
if (argc == 2 && std::strcmp(argv[1], "--image-atomic64-only") == 0) {
|
||||
VulkanHarness vulkan;
|
||||
RunCase(&vulkan, ImageAtomicUMaxGlcAndExec<false>());
|
||||
RunCase(&vulkan, ImageAtomicUMaxGlcAndExec<true>());
|
||||
for (const auto &atomic : ImageAtomicIntegerCases) {
|
||||
RunCase(&vulkan, ImageAtomicIntegerGlcAndExec(atomic, false));
|
||||
RunCase(&vulkan, ImageAtomicIntegerGlcAndExec(atomic, true));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
if (argc == 2 && std::strcmp(argv[1], "--ds-atomics-only") == 0) {
|
||||
|
|
|
|||
|
|
@ -4413,25 +4413,32 @@ void TestImageAtomicWidthDecoder() {
|
|||
decoded.dst.reg == 2u && decoded.dmask == 3u && !decoded.glc,
|
||||
"captured image atomic lost its 64-bit data width");
|
||||
|
||||
for (const auto opcode : {0x10u, 0x17u}) {
|
||||
for (const auto opcode : {0x0fu, 0x10u, 0x11u, 0x14u, 0x15u, 0x16u,
|
||||
0x17u, 0x18u, 0x19u, 0x1au, 0x1eu, 0x1fu}) {
|
||||
const bool compare_swap = opcode == 0x10u;
|
||||
const bool supports_64 = opcode != 0x10u && opcode != 0x14u &&
|
||||
opcode != 0x16u && opcode != 0x1eu && opcode != 0x1fu;
|
||||
for (uint32_t mask = 0; mask < 16u; ++mask) {
|
||||
const uint32_t words[] = {EncodeMimg0(opcode, mask), captured[1]};
|
||||
DecodeInstruction(words, 0, decoded);
|
||||
const bool compare_swap = opcode == 0x10u;
|
||||
const bool supported = mask == (compare_swap ? 3u : 1u) ||
|
||||
(!compare_swap && mask == 3u);
|
||||
Check((decoded.opcode != Opcode::UNSUPPORTED) == supported,
|
||||
"image atomic accepted an invalid or unsupported width mask");
|
||||
if (supported) {
|
||||
Check(decoded.data_bits == (!compare_swap && mask == 3u ? 64u : 32u),
|
||||
"image atomic DMASK selected the wrong data width");
|
||||
for (const bool glc : {false, true}) {
|
||||
const uint32_t words[] = {EncodeMimg0(opcode, mask, glc), captured[1]};
|
||||
DecodeInstruction(words, 0, decoded);
|
||||
const bool supported = mask == (compare_swap ? 3u : 1u) ||
|
||||
(supports_64 && mask == 3u);
|
||||
Check((decoded.opcode != Opcode::UNSUPPORTED) == supported,
|
||||
"image atomic accepted an invalid or unsupported width mask");
|
||||
if (supported) {
|
||||
const auto bits = !compare_swap && mask == 3u ? 64u : 32u;
|
||||
Check(decoded.data_bits == bits && decoded.glc == glc &&
|
||||
decoded.data_dwords == (compare_swap ? 2u : bits / 32u),
|
||||
"image atomic DMASK selected the wrong data width or return mode");
|
||||
}
|
||||
const uint32_t d16_words[] = {words[0], words[1] | (1u << 31u)};
|
||||
DecodeInstruction(d16_words, 0, decoded);
|
||||
Check(decoded.opcode == Opcode::UNSUPPORTED,
|
||||
"image atomic incorrectly accepted D16 data");
|
||||
}
|
||||
}
|
||||
}
|
||||
const uint32_t unsupported[] = {EncodeMimg0(0x11u, 3u), captured[1]};
|
||||
DecodeInstruction(unsupported, 0, decoded);
|
||||
Check(decoded.opcode == Opcode::UNSUPPORTED && decoded.data_bits == 64u,
|
||||
"unsupported 64-bit image atomic silently decoded as 32-bit");
|
||||
}
|
||||
|
||||
void TestNewShaderDecoderArchitecture() {
|
||||
|
|
|
|||
Loading…
Reference in New Issue