shader: support RDNA2 BVH64 ray intersections with shared traversal
This commit is contained in:
nmzik
parent
33e74cab2c
commit
dbf66b7f4f
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@ -226,13 +226,13 @@ void DefineBvhIntersect(EmitterState& s) {
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if (!s.requirements.bvh) return;
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const auto u = TypeU32(s), f = TypeF32(s), b = TypeBool(s), wide = TypeScalarU64(s);
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const auto vec4 = TypeU32Vector(s, 4), vec3 = TypeF32Vector(s, 3);
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const auto signature = s.builder.Type(spv::OpTypeFunction, vec4, vec4, u, f, vec3, vec3, vec3);
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const auto signature = s.builder.Type(spv::OpTypeFunction, vec4, vec4, wide, f, vec3, vec3, vec3);
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s.bvh_intersect_function = s.builder.AllocateId();
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s.builder.AddName(s.bvh_intersect_function, "bvh_intersect");
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s.builder.AddFunction(spv::OpFunction, vec4, s.bvh_intersect_function,
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spv::FunctionControlMaskNone, signature);
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std::array<uint32_t, 6> args;
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const std::array types {vec4, u, f, vec3, vec3, vec3};
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const std::array types {vec4, wide, f, vec3, vec3, vec3};
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for (uint32_t i = 0; i < args.size(); ++i) {
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args[i] = s.builder.AllocateId();
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s.builder.AddFunction(spv::OpFunctionParameter, types[i], args[i]);
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@ -253,7 +253,7 @@ void DefineBvhIntersect(EmitterState& s) {
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const auto shr = [&](uint32_t value, uint32_t shift) {
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return Binary(s, spv::OpShiftRightLogical, u, value, ConstantU32(s, shift));
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};
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const auto kind = and_bits(node, 7);
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const auto kind = and_bits(Unary(s, spv::OpUConvert, u, node), 7);
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const auto triangle = Binary(s, spv::OpULessThan, b, kind, ConstantU32(s, 4));
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const auto full = Binary(s, spv::OpIEqual, b, kind, ConstantU32(s, 5));
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const auto half = Binary(s, spv::OpIEqual, b, kind, ConstantU32(s, 4));
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@ -262,7 +262,7 @@ void DefineBvhIntersect(EmitterState& s) {
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const auto grow = and_bits(shr(words[1], 23), 0xff);
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const auto base = Binary(s, spv::OpShiftLeftLogical, wide,
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DeviceAddressFromWords(s, words[0], and_bits(words[1], 0xff)), ConstantDeviceAddress(s, 8));
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const auto index = Unary(s, spv::OpUConvert, wide, shr(node, 3));
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const auto index = Binary(s, spv::OpShiftRightLogical, wide, node, ConstantDeviceAddress(s, 3));
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const auto last_index = Binary(s, spv::OpIAdd, wide, index,
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Select(s, wide, full, ConstantDeviceAddress(s, 1), ConstantDeviceAddress(s, 0)));
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const auto address = Binary(s, spv::OpIAdd, wide, base,
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@ -325,17 +325,23 @@ void DefineBvhIntersect(EmitterState& s) {
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uint32_t EmitBvhIntersect(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& s = ctx.state;
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const auto* ray = ctx.ImageAddress(inst.Arg(1));
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if (ray == nullptr || ray->NumArgs() < 11 || s.bvh_intersect_function == 0)
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ctx.Fail(inst, "BVH intersection requires eleven address components and its shared function");
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const auto node_words = inst.Flags<uint32_t>();
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if (ray == nullptr || (node_words != 1u && node_words != 2u) ||
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ray->NumArgs() < node_words + 10u || s.bvh_intersect_function == 0)
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ctx.Fail(inst, "BVH intersection requires its node pointer, ray components and shared function");
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const auto vector = [&](uint32_t first) {
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Vec3 values;
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for (uint32_t i = 0; i < 3; ++i)
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values[i] = Unary(s, spv::OpBitcast, TypeF32(s), ctx.Arg(*ray, first + i));
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return Vector(s, TypeF32Vector(s, 3), values);
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};
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const auto descriptor = ctx.Arg(inst, 0), node = ctx.Arg(*ray, 0);
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const auto extent = Unary(s, spv::OpBitcast, TypeF32(s), ctx.Arg(*ray, 1));
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const auto origin = vector(2), direction = vector(5), inverse = vector(8);
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const auto descriptor = ctx.Arg(inst, 0);
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const auto node = node_words == 2u
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? DeviceAddressFromWords(s, ctx.Arg(*ray, 0), ctx.Arg(*ray, 1))
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: Unary(s, spv::OpUConvert, TypeScalarU64(s), ctx.Arg(*ray, 0));
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const auto extent = Unary(s, spv::OpBitcast, TypeF32(s), ctx.Arg(*ray, node_words));
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const auto origin = vector(node_words + 1u), direction = vector(node_words + 4u),
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inverse = vector(node_words + 7u);
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return EmitValueOrDefaultIfCondition(s, ctx.Arg(inst, 2), TypeU32Vector(s, 4),
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ConstantU32CompositeZero(s, 4), [&] {
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const auto result = s.builder.AllocateId();
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@ -228,7 +228,8 @@ Opcode DecodeMimgOpcode(uint32_t opcode, const MimgSampleInfo* sample, const Mim
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case 0x09u: return Opcode::IMAGE_STORE_MIP;
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case 0x0eu: return Opcode::IMAGE_GET_RESINFO;
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case 0x60u: return Opcode::IMAGE_GET_LOD;
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case 0xe6u: return Opcode::IMAGE_BVH_INTERSECT_RAY;
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case 0xe6u:
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case 0xe7u: return Opcode::IMAGE_BVH_INTERSECT_RAY;
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default: return Opcode::UNSUPPORTED;
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}
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}
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@ -258,6 +259,7 @@ uint32_t DecodeMimgAddressComponents(uint32_t opcode, ImageDimension dimension,
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switch (opcode) {
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case 0xe6u: return 11u;
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case 0xe7u: return 12u;
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case 0x0eu: return 1u;
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case 0x01u:
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case 0x09u: return ImageCoordComponents(dimension) + 1u;
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@ -379,10 +381,10 @@ void DecodeMimg(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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if (d16 && !supports_d16) {
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SetUnsupported(inst, Family::MIMG, opcode, "MIMG opcode does not support D16 data");
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}
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if (opcode == 0xe6u &&
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if (inst.opcode == Opcode::IMAGE_BVH_INTERSECT_RAY &&
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(a16 || !r128 || inst.dmask != 0xfu || (nsa_dwords != 0u && nsa_dwords != 3u))) {
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SetUnsupported(inst, Family::MIMG, opcode,
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"BVH intersection requires eleven full-float ray DWORDs and R128/dmask:0xf");
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"BVH intersection requires full-float ray DWORDs and R128/dmask:0xf");
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}
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DecodeVectorGpr(vdata, inst.dst);
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@ -905,7 +905,8 @@ void Translator::EmitMemory(const Decoder::Instruction& inst) {
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switch (inst.opcode) {
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case Decoder::Opcode::IMAGE_BVH_INTERSECT_RAY: {
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const auto result = ir.Emit(IR::ValueOpcode::BvhIntersect,
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{ConstructU32x4(inst.src1, 4), MakeImageAddress(inst, inst.src0), ir.GetExec()});
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{ConstructU32x4(inst.src1, 4), MakeImageAddress(inst, inst.src0), ir.GetExec()},
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inst.image_address_components - 10u);
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for (uint32_t component = 0; component < 4; ++component) {
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WriteOperand(OffsetOperand(inst.dst, component),
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ir.Emit(IR::ValueOpcode::CompositeExtractU32x4, {result, IR::Value(component)}));
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@ -83,13 +83,15 @@ TestCase FlatStackApertures(u32 wave_size) {
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return test;
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}
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TestCase BvhIntersections(bool barycentrics, bool sorted, u32 grow = 0) {
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TestCase BvhIntersections(bool barycentrics, bool sorted, u32 grow = 0, bool wide = false) {
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TestCase test;
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test.name = barycentrics ? (sorted ? "BvhBarycentricSorted" : "BvhBarycentricUnsorted")
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: (sorted ? "BvhTriangleIdSorted" : "BvhTriangleIdUnsorted");
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if (grow != 0) test.name = "BvhBoxExitGrowth";
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if (wide) test.name = "Bvh64HighNodePointers";
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constexpr u32 NodeStart = 1024, OutputStart = 512, LaneCount = 32;
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constexpr uint64_t GuestBase = 0x10000;
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const u32 node_base = wide ? 1u << 29 : 0;
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const auto bits = [](float value) { return std::bit_cast<u32>(value); };
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constexpr u32 Infinity = 0x7f800000, Invalid = UINT32_MAX, Flag = 0x04040404;
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test.initial.resize(NodeStart + 258 * 16);
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@ -183,6 +185,19 @@ TestCase BvhIntersections(bool barycentrics, bool sorted, u32 grow = 0) {
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} else if (lane == 29) {
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data[input] = (255 << 3) | 5;
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}
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if (wide) {
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// Keep the same small backing while placing nodes beyond the 32-bit pointer range.
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std::copy_backward(data.begin() + input + 1, data.begin() + input + 11,
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data.begin() + input + 12);
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data[input + 1] = 1;
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if (lane == 14 || lane == 15) {
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data[input] = lane == 14 ? 0 : 5;
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// Neither an oversized index nor a shifted-address wrap may read node zero.
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data[input + 1] = lane == 14 ? 0x00001000 : 0x20000000;
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expected[lane] = lane == 14 ? std::array<u32, 4>{Infinity, bits(1), Invalid, 0}
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: std::array<u32, 4>{Invalid, Invalid, Invalid, Invalid};
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}
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}
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}
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test.expected = test.initial;
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for (u32 lane = 0; lane < LaneCount; ++lane) {
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@ -198,29 +213,31 @@ TestCase BvhIntersections(bool barycentrics, bool sorted, u32 grow = 0) {
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// The resource is a GPU value, not a materialized host image descriptor.
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AppendSMovLiteral(&code, 8, GuestBase >> 8);
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AppendSMovLiteral(&code, 9, (sorted ? 0x80000000 : 0) | (grow << 23));
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AppendSMovLiteral(&code, 10, 256);
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AppendSMovLiteral(&code, 10, node_base + 256);
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AppendSMovLiteral(&code, 11, barycentrics ? 0x81000000 : 0x80000000);
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code.push_back(EncodeVop2(0x1a, 1, InlineU32(6), 0));
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for (u32 offset : {0u, 4u, 8u}) {
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code.insert(code.end(), {EncodeMubuf0(offset == 8 ? 0x0f : 0x0e, offset * 4),
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code.insert(code.end(), {EncodeMubuf0(offset == 8 && !wide ? 0x0f : 0x0e, offset * 4),
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EncodeMubuf1(4 + offset, 0, 1)});
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}
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code.insert(code.end(), {EncodeMimg0(0xe6, 15, 0, false, 0, true),
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code.insert(code.end(), {EncodeMimg0(wide ? 0xe7 : 0xe6, 15, 0, false, 0, true),
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EncodeMimg1(20, 4, 2)});
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code.push_back(EncodeVop2(0x1a, 2, InlineU32(2), 0));
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for (u32 i = 0; i < 4; ++i) AppendStoreVgprAtLaneDwordOffset(&code, 20 + i, 2, OutputStart + i);
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// NSA addressing, the FP32 second-block bound, and inactive destination lanes.
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AppendSMovLiteral(&code, 10, 2);
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AppendSMovLiteral(&code, 10, node_base + 2);
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for (u32 i = 0; i < 4; ++i) AppendVMovLiteral(&code, 24 + i, 0x12345678 + i);
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AppendSMovLiteral(&code, 126, 0x000fffff);
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code.insert(code.end(), {EncodeMimg0(0xe6, 15, 3, false, 0, true),
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EncodeMimg1(24, 4, 2), 0x08070605, 0x0c0b0a09, 0x00000e0d});
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code.insert(code.end(), {EncodeMimg0(wide ? 0xe7 : 0xe6, 15, 3, false, 0, true),
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EncodeMimg1(24, 4, 2), 0x08070605, 0x0c0b0a09,
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wide ? 0x000f0e0du : 0x00000e0du});
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code.push_back(EncodeSop1(0x04, 126, 193));
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for (u32 i = 0; i < 4; ++i)
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AppendStoreVgprAtLaneDwordOffset(&code, 24 + i, 2, OutputStart + LaneCount * 4 + i);
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AppendEnd(&code);
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test.bda_mappings = {{GuestBase, NodeStart * sizeof(u32)},
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{GuestBase + 0x4000, (NodeStart + 257 * 16) * sizeof(u32)}};
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const auto nodes_address = GuestBase + (uint64_t{node_base} << 6);
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test.bda_mappings = {{nodes_address, NodeStart * sizeof(u32)},
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{nodes_address + 0x4000, (NodeStart + 257 * 16) * sizeof(u32)}};
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test.compute_info.wave_size = LaneCount;
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test.compute_info.threads_num[0] = LaneCount;
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test.compute_info.threads_num[1] = test.compute_info.threads_num[2] = 1;
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@ -5,10 +5,15 @@ void TestRayTracingInstructions() {
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EncodeMubuf0(0x1e, 0, false), EncodeMubuf1(16, 0, 0),
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0xf1989f07u, 0x00071001u, 0x3d3e3c15u, 0x38095851u, 0x00003a39u,
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EncodeMubuf0(0x1e, 16, false), EncodeMubuf1(16, 0, 0),
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0xf19c9f01u, 0x00081014u,
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EncodeMubuf0(0x1e, 32, false), EncodeMubuf1(16, 0, 0),
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// Captured 016c1ab44ee6a526: pointer v2:v7 and final inverse component v5.
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0xf19c9f07u, 0x00090202u, 0x28263607u, 0x221f1e29u, 0x00050403u,
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EncodeMubuf0(0x1e, 48, false), EncodeMubuf1(2, 0, 0),
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EncodeSopp(0x01)};
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D::Program decoded;
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D::DecodeProgram(code, decoded);
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Check(decoded.instructions.size() == 5 &&
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Check(decoded.instructions.size() == 9 &&
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decoded.instructions.back().opcode == D::Opcode::S_ENDPGM,
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"decoder stopped before instructions following BVH intersections");
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for (const auto index : {0u, 2u}) {
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@ -17,10 +22,20 @@ void TestRayTracingInstructions() {
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inst.image_address_components == 11 && inst.data_dwords == 4 && inst.image_r128,
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"BVH32 instruction lost its ray or descriptor width");
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}
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for (const auto index : {4u, 6u}) {
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const auto &inst = decoded.instructions[index];
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Check(inst.opcode == D::Opcode::IMAGE_BVH_INTERSECT_RAY && inst.opcode_id == 0xe7 &&
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inst.image_address_components == 12 && inst.data_dwords == 4 && inst.image_r128,
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"BVH64 instruction lost its full node pointer or ray width");
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}
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Check(decoded.instructions[6].word_count == 5 &&
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decoded.instructions[6].image_nsa_addr[0] == 7 &&
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decoded.instructions[6].image_nsa_addr[10] == 5,
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"captured BVH64 NSA pointer or final ray component was not decoded");
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Check(decoded.instructions[2].image_nsa_addr[9] == 58,
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"BVH NSA ray components were not decoded");
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const auto result = RecompileForTest(code, MakeCompileOptions(ShaderType::Compute));
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Check(CountSourceOccurrences(result.ir_dump, "BvhIntersect") == 2 &&
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Check(CountSourceOccurrences(result.ir_dump, "BvhIntersect") == 4 &&
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result.program.info.uses_dma && result.program.info.images.empty() &&
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result.program.info.samplers.empty(),
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"BVH intersections did not use GPU descriptors and raw guest memory");
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@ -31,20 +46,22 @@ void TestRayTracingInstructions() {
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Check(decoded.instructions.size() == 2 && decoded.instructions[0].opcode == D::Opcode::S_MOV_B32,
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"BVH-shaped scalar literal was decoded as an instruction");
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#if KYTY_PLATFORM != KYTY_PLATFORM_WINDOWS
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for (const auto words : {std::array{0xf19c9f01u, 0x00081014u}, // BVH64
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std::array{0xf1989f01u, 0x40081014u}, // A16
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for (const auto words : {std::array{0xf19c9f01u, 0x40081014u}, // BVH64 A16
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std::array{0xf1989f01u, 0x40081014u}, // BVH32 A16
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std::array{0xf1981f01u, 0x00081014u}, // not R128
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std::array{0xf1989f01u, 0x80081014u}}) { // D16
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const std::array unsupported{words[0], words[1], EncodeSopp(0x01)};
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ExpectFatal([&]() { (void)RecompileForTest(unsupported, MakeCompileOptions(ShaderType::Compute)); },
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"unsupported BVH encoding was silently accepted");
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}
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for (const auto nsa : {1u, 2u}) {
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std::array<uint32_t, 5> truncated{0xf1989f01u | (nsa << 1), 0x00081014u};
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truncated[2 + nsa] = EncodeSopp(0x01);
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ExpectFatal([&]() {
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(void)RecompileForTest(std::span(truncated).first(3 + nsa), MakeCompileOptions(ShaderType::Compute));
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}, "BVH NSA instruction accepted fewer than eleven ray addresses");
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for (const auto encoding : {0xf1989f01u, 0xf19c9f01u}) {
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for (const auto nsa : {1u, 2u}) {
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std::array<uint32_t, 5> truncated{encoding | (nsa << 1), 0x00081014u};
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truncated[2 + nsa] = EncodeSopp(0x01);
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ExpectFatal([&]() {
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(void)RecompileForTest(std::span(truncated).first(3 + nsa), MakeCompileOptions(ShaderType::Compute));
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}, "BVH NSA instruction accepted an incomplete ray address");
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}
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}
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#endif
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}
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@ -33248,6 +33248,7 @@ std::vector<TestCase> MakeCases() {
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cases.push_back(FlatStackApertures(32));
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cases.push_back(FlatStackApertures(64));
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cases.push_back(BvhIntersections(true, true, 1));
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cases.push_back(BvhIntersections(true, true, 0, true));
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for (bool barycentrics : {false, true}) {
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for (bool sorted : {false, true}) {
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cases.push_back(BvhIntersections(barycentrics, sorted));
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@ -38481,6 +38482,7 @@ int main(int argc, char **argv) {
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RunCase(&vulkan, FlatStackApertures(32));
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RunCase(&vulkan, FlatStackApertures(64));
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RunCase(&vulkan, BvhIntersections(true, true, 1));
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RunCase(&vulkan, BvhIntersections(true, true, 0, true));
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for (bool barycentrics : {false, true}) {
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for (bool sorted : {false, true}) {
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RunCase(&vulkan, BvhIntersections(barycentrics, sorted));
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