fix(agc): implement sceAgcGetGsOversubscription (#1083)
* Implement AGC GS oversubscription descriptor output * fix(agc): drop the Yotei 0x191/0x192 register workaround Ghost of Yotei 2.002 submitted two register descriptors whose output sceAgcGetGsOversubscription left uninitialized, so it wrote user-config 0x191 and shader 0x192, registers gfx10 does not define. The export now fills the descriptors (user-config 0x260 and shader 0x81), so those writes no longer happen. Remove the workaround that accepted and ignored both registers, together with its logging and the two tests that pinned it. An unknown register in either table is a fatal error again, which the export's own tests rely on. Ghost of Yotei 2.0 starts and presents its first frame with this change and the export from #1083. --------- Co-authored-by: foufouadi <attar.foued@gmail.com>
This commit is contained in:
Ainesh M.
GitHub
parent
b307b2f8fd
commit
7ebf642aff
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@ -0,0 +1,140 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Gpu.GpuCommands.Registers;
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namespace SharpEmu.Libs.Agc;
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public static partial class AgcExports
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{
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[SysAbiExport(
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Nid = "NKIzURsgV7I",
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ExportName = "sceAgcGetGsOversubscription",
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Target = Generation.Gen5,
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LibraryName = "libSceAgcDriver")]
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public static int GetGsOversubscription(CpuContext ctx)
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{
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var output = ctx[CpuRegister.Rdi];
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var shader = ctx[CpuRegister.Rsi];
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var budget = (uint)ctx[CpuRegister.Rdx];
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if (output == 0)
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{
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return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT);
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}
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var pcAllocation = 0u;
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var lateAllocation = 0u;
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// These endpoints initialize both descriptors without dereferencing the shader.
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if (budget == uint.MaxValue)
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{
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pcAllocation = 0x7FF;
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lateAllocation = 0x7F_0000;
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}
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else if (budget != 0)
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{
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ctx.GetXmmRegister(0, out var factorBits, out _);
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var factor = BitConverter.UInt32BitsToSingle((uint)factorBits);
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if (!float.IsFinite(factor) ||
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!TryGetGsOccupancy(ctx, shader, out var stages, out var baseline, out var expanded))
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{
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return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT);
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}
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var minimum = Math.Min(baseline.Vertex, baseline.Export);
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var waveShift = (stages & 0x0040_0000) != 0 ? 5 : 6;
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var maximum = Math.Min(Math.Min(expanded.Vertex, expanded.Export), Math.Min(budget >> waveShift, 1024));
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var headroom = maximum > minimum ? maximum - minimum : 0;
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var scaled = MathF.FusedMultiplyAdd(factor, headroom, minimum);
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if (!(scaled >= 0 && scaled < 4294967296f))
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{
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return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT);
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}
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var target = (uint)scaled;
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if (target > minimum && target < baseline.Export)
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{
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var range = Math.Max(expanded.Vertex - baseline.Vertex, 1);
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var lines = Math.Max(Math.Min(((ulong)(target - baseline.Vertex) << 10) / range, 1024), 1);
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pcAllocation = ((uint)lines * 2 - 1) & 0x7FF;
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lateAllocation = 0x7F_0000;
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}
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else if (target > minimum)
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{
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var range = Math.Max(expanded.Export - baseline.Export, 1);
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var waves = Math.Min((ulong)(target - baseline.Export) * 127 / range, 127);
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pcAllocation = 0x7FF;
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lateAllocation = (uint)waves << 16;
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}
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}
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// The result is two bank-specific register descriptors, not two scalar values.
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Span<byte> registers = stackalloc byte[16];
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BinaryPrimitives.WriteUInt32LittleEndian(registers, UserConfigRegisterOffset.ParameterOversubscription);
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BinaryPrimitives.WriteUInt32LittleEndian(registers[4..], pcAllocation);
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BinaryPrimitives.WriteUInt32LittleEndian(registers[8..], ShaderRegisterOffset.SpiShaderPgmRsrc4Gs);
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BinaryPrimitives.WriteUInt32LittleEndian(registers[12..], lateAllocation);
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if (!ctx.Memory.TryWrite(output, registers))
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{
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return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT);
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}
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TraceAgc($"agc.gs_oversubscription output=0x{output:X16} shader=0x{shader:X16} budget={budget} pc_alloc=0x{pcAllocation:X8} late_alloc=0x{lateAllocation:X8}");
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return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_OK);
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}
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private readonly record struct GsOccupancy(uint Vertex, uint Export);
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private static bool TryGetGsOccupancy(CpuContext ctx, ulong shader, out uint stages, out GsOccupancy baseline, out GsOccupancy expanded)
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{
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stages = 0;
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baseline = expanded = default;
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if (shader == 0 ||
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!TryReadUInt64(ctx, shader + ShaderCxRegistersOffset, out var table) || table == 0 ||
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!TryReadByte(ctx, shader + 0x5B, out var count) ||
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!TryReadUInt64(ctx, shader + ShaderSpecialsOffset, out var specials) || specials == 0 ||
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!TryReadUInt32(ctx, specials + 12, out stages))
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{
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return false;
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}
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uint onchip = 0, subgroup = 0, vertexOutput = 0, clipOutput = 0, maxOutput = 0;
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var found = 0;
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for (var index = 0; index < count; index++)
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{
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if (!TryReadUInt32(ctx, table + (ulong)index * 8, out var offset) ||
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!TryReadUInt32(ctx, table + (ulong)index * 8 + 4, out var value))
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{
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return false;
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}
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switch (offset)
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{
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case ContextRegisterOffset.VgtGsOnchipCntl: onchip = value; found |= 1; break;
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case ContextRegisterOffset.GeNggSubgroupCntl: subgroup = value; found |= 2; break;
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case ContextRegisterOffset.SpiVsOutConfig: vertexOutput = value; found |= 4; break;
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case ContextRegisterOffset.PaClVsOutCntl: clipOutput = value; found |= 8; break;
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case ContextRegisterOffset.GeMaxOutputPerSubgroup: maxOutput = value; found |= 16; break;
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}
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}
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var outputWords = ((maxOutput & 0x3FF) + 31) >> 5;
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if (found != 31 || outputWords == 0)
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{
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return false;
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}
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var work = ((((onchip >> 11) & 0x7FF) * (subgroup & 0x1FF)) + 31) >> 5;
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var waves = Math.Max(work, outputWords);
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if ((stages & 0x0040_0000) == 0) waves >>= 1;
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waves = Math.Max(waves, 1);
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var exports = 1 + ((clipOutput >> 21) & 1) + ((clipOutput >> 22) & 1) + ((clipOutput >> 23) & 1);
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var parameters = ((vertexOutput >> 2) & 0xF) + 1;
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var vertexCapacity = (vertexOutput & 0x80) != 0 ? 2048 : 1024 / parameters;
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var expandedVertexCapacity = (vertexOutput & 0x80) != 0 ? 2048 : 2048 / parameters;
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baseline = new GsOccupancy(waves * (vertexCapacity / outputWords), waves * ((128 / exports * 4) / outputWords));
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expanded = new GsOccupancy(waves * (expandedVertexCapacity / outputWords), waves * ((382 / exports * 4) / outputWords));
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return true;
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}
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}
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@ -205,9 +205,6 @@ public static class ShaderRegisterOffset
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public const uint SpiShaderUserAccumLsHs0 = 0x132;
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public const uint SpiShaderPgmLoLs = 0x148;
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public const uint SpiShaderPgmHiLs = 0x149;
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// Past the LS block, where gfx10 documents no register. Ghost of Yotei 2.002 writes 1 here
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// from a shader register table at startup; no shader state depends on it.
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public const uint SpiShaderUndocumented192 = 0x192;
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public const uint ComputeStartX = 0x204;
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public const uint ComputeStartY = 0x205;
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public const uint ComputeStartZ = 0x206;
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@ -230,8 +227,6 @@ public static class ShaderRegisterOffset
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public static class UserConfigRegisterOffset
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{
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// Below the primitive-assembly block, where gfx10 to gfx12 document no register. Ghost of
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// Yotei 2.002 writes 0 here from a user-config table, next to shader register 0x192.
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public const uint UserConfigUndocumented191 = 0x191;
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public const uint VgtPrimitiveType = 0x242;
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public const uint VgtIndexType = 0x243;
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public const uint VgtObjectId = 0x248;
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@ -66,8 +66,6 @@ internal static partial class RegisterWriters
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indirect[offset] = IgnoreEntry;
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}
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indirect[SpiShaderUndocumented192] = UndocumentedShaderEntry;
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direct[SpiGraphicsShaderControlPs] = ForwardShaderPacket;
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direct[SpiGraphicsShaderControlGs] = ForwardShaderPacket;
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direct[SpiShaderUserDataAddrLoGs] = ForwardShaderPacket;
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@ -106,18 +104,6 @@ internal static partial class RegisterWriters
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indirect[SpiShaderPgmRsrc1Vs] = static (banks, _, value) => banks.Shader.Vertex.LegacyVertexResource1 = value;
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indirect[SpiShaderPgmRsrc2Vs] = static (banks, _, value) => banks.Shader.Vertex.LegacyVertexResource2 = value;
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}
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// The value is not applied, but each new one is logged so a rendering difference can be traced to it.
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private static long _lastUndocumentedShaderValue = -1;
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private static void UndocumentedShaderEntry(RegisterBanks banks, uint offset, uint value)
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{
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if (Interlocked.Exchange(ref _lastUndocumentedShaderValue, value) != value)
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{
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Console.Error.WriteLine($"[GPU][WARN] Undocumented shader register written: offset=0x{offset:X4} value=0x{value:X8}; it is not applied.");
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}
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}
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private static uint PixelUserScalarsPacket(RegisterBanks banks, in PacketContext packet, uint offset, ReadOnlySpan<uint> values) =>
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UserScalarsPacket(banks, in packet, offset, values, banks.Shader.Pixel.UserScalars, SpiShaderUserDataPs0, GraphicsUserScalarCount);
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@ -50,19 +50,7 @@ internal static partial class RegisterWriters
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indirect[GdsOaCounter] = OrderedAppendEntry;
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indirect[GdsOaAddress] = OrderedAppendEntry;
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indirect[GeStereoCntl] = IgnoreEntry;
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indirect[UserConfigUndocumented191] = UndocumentedUserConfigEntry;
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}
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private static long _lastUndocumentedUserConfigValue = -1;
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private static void UndocumentedUserConfigEntry(RegisterBanks banks, uint offset, uint value)
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{
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if (Interlocked.Exchange(ref _lastUndocumentedUserConfigValue, value) != value)
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{
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Console.Error.WriteLine($"[GPU][WARN] Undocumented user-config register written: offset=0x{offset:X4} value=0x{value:X8}; it is not applied.");
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}
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}
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private static uint PrimitiveTypePacket(RegisterBanks banks, in PacketContext packet, uint offset, ReadOnlySpan<uint> values) =>
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SingleValue(banks, in packet, offset, values, PrimitiveTypeEntry);
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@ -0,0 +1,144 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using SharpEmu.HLE;
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using SharpEmu.Libs.Gpu.GpuCommands;
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using SharpEmu.Libs.Tests.Gpu.GpuCommands;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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public sealed class AgcGsOversubscriptionTests
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{
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private const string Nid = "NKIzURsgV7I";
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private const ulong Table = StreamRunner.TableAddress;
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private static ModuleManager Manager()
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{
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var manager = new ModuleManager();
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manager.RegisterExports(SharpEmu.Generated.SysAbiExportRegistry.CreateExports(Generation.Gen5));
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return manager;
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}
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[Fact]
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public void ZeroBudget_ReplacesStaleDescriptorsBeforeNativeRegisterSubmission()
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{
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var runner = new StreamRunner();
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runner.Host.WriteWords(Table, [0x191, 0, 0x192, 1]);
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var context = new CpuContext(runner.Host.Memory, Generation.Gen5);
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context[CpuRegister.Rdi] = Table;
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context[CpuRegister.Rsi] = ulong.MaxValue; // The zero-budget contract needs no shader read.
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context[CpuRegister.Rdx] = 0;
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// Yotei ignores the return value and submits both output descriptors.
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var result = Manager().Dispatch(Nid, context);
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runner.Run(
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StreamRunner.Packet(PacketOpcode.SetUserConfigRegisterIndirect, StreamRunner.Low(Table), StreamRunner.High(Table), 0x8000_0000, 1),
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StreamRunner.Packet(PacketOpcode.SetShaderRegisterIndirect, StreamRunner.Low(Table + 8), StreamRunner.High(Table + 8), 0x8000_0000, 1));
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(0u, runner.Interpreter.Registers.Shader[0x81]);
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Assert.False(runner.Interpreter.Registers.Shader.ContainsKey(0x192));
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}
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[Fact]
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public void Export_IsRegisteredForTheDriverLibrary()
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{
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Assert.True(Manager().TryGetExport(Nid, out var export));
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Assert.Equal("sceAgcGetGsOversubscription", export.Name);
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Assert.Equal("libSceAgcDriver", export.LibraryName);
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Assert.Equal(Generation.Gen5, export.Target);
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}
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[Theory]
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[InlineData(0u, 0u, 0u)]
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[InlineData(uint.MaxValue, 0x7FFu, 0x7F_0000u)]
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public void BudgetEndpoints_InitializeBothOffsetsAndValuesWithoutShaderReads(uint budget, uint pc, uint late)
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{
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var runner = new StreamRunner();
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runner.Host.WriteWords(Table, [0x191, 0xDEAD, 0x192, 0xBEEF]);
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var context = Context(runner, budget);
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context[CpuRegister.Rsi] = ulong.MaxValue;
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context.SetXmmRegister(0, BitConverter.SingleToUInt32Bits(float.NaN), 0);
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_OK, Manager().Dispatch(Nid, context));
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AssertOutput(context, pc, late);
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Assert.Equal(0UL, context[CpuRegister.Rax]);
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}
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[Theory]
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[InlineData(0u, 65536u, 0.5f, 0x0040_0000u, 0x7FFu, 0x20_0000u)]
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[InlineData(0u, 65536u, 0f, 0x0040_0000u, 0u, 0u)]
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[InlineData(0x3Cu, 4096u, 0.5f, 0x0040_0000u, 0x3FFu, 0x7F_0000u)]
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[InlineData(0x3Cu, 4096u, 0.5f, 0u, 0u, 0u)]
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public void FiniteBudget_UsesShaderOccupancyAndWaveSize(uint vertexOutput, uint budget, float factor, uint stages, uint pc, uint late)
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{
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var runner = new StreamRunner();
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var context = Context(runner, budget);
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WriteShader(runner, context, vertexOutput, stages);
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context.SetXmmRegister(0, BitConverter.SingleToUInt32Bits(factor), 0);
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_OK, Manager().Dispatch(Nid, context));
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AssertOutput(context, pc, late);
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}
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[Fact]
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public void InvalidShaderAndFactor_DoNotPartiallyOverwriteOutput()
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{
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var runner = new StreamRunner();
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runner.Host.WriteWords(Table, [0x191, 0xDEAD, 0x192, 0xBEEF]);
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var context = Context(runner, 65536);
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT, Manager().Dispatch(Nid, context));
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WriteShader(runner, context, 0, 0x0040_0000);
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context.SetXmmRegister(0, BitConverter.SingleToUInt32Bits(float.NaN), 0);
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT, Manager().Dispatch(Nid, context));
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Assert.True(context.TryReadUInt32(Table, out var offset));
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Assert.Equal(0x191u, offset);
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Assert.True(context.TryReadUInt32(Table + 12, out var value));
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Assert.Equal(0xBEEFu, value);
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}
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[Fact]
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public void InvalidOutput_ReturnsAnErrorAndUnknownUcWritesRemainFatal()
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{
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var runner = new StreamRunner();
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var context = Context(runner, 0);
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context[CpuRegister.Rdi] = 0;
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT, Manager().Dispatch(Nid, context));
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context[CpuRegister.Rdi] = ulong.MaxValue;
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Assert.Equal(OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT, Manager().Dispatch(Nid, context));
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runner.Host.WriteWords(Table, [0x191, 0]);
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Assert.Contains("user-config table register is not supported", runner.RunExpectingFatal(
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StreamRunner.Packet(PacketOpcode.SetUserConfigRegisterIndirect, StreamRunner.Low(Table), StreamRunner.High(Table), 0x8000_0000, 1)).Message);
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}
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private static CpuContext Context(StreamRunner runner, uint budget)
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{
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var context = new CpuContext(runner.Host.Memory, Generation.Gen5);
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context[CpuRegister.Rdi] = Table;
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context[CpuRegister.Rdx] = budget;
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return context;
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}
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private static void WriteShader(StreamRunner runner, CpuContext context, uint vertexOutput, uint stages)
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{
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var shader = Table + 0x100;
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var registers = Table + 0x200;
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var specials = Table + 0x300;
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runner.Host.WriteQword(shader + 0x18, registers);
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runner.Host.WriteQword(shader + 0x28, specials);
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Assert.True(runner.Host.Memory.TryWrite(shader + 0x5B, new byte[] { 5 }));
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runner.Host.WriteWords(registers, [0x291, 1 << 11, 0x2D3, 32, 0x1B1, vertexOutput, 0x207, 0, 0x1FF, 32]);
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runner.Host.WriteWords(specials + 12, [stages]);
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context[CpuRegister.Rsi] = shader;
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}
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private static void AssertOutput(CpuContext context, uint pc, uint late)
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{
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var expected = new uint[] { 0x260, pc, 0x81, late };
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for (var index = 0; index < expected.Length; index++)
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{
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Assert.True(context.TryReadUInt32(Table + (ulong)index * 4, out var actual));
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Assert.Equal(expected[index], actual);
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}
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}
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}
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@ -48,27 +48,6 @@ public sealed class RegisterWriteTableTests
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Assert.Equal(0x1111u, banks.Shader.Vertex.HullUserScalars.Values[0]);
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}
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[Fact]
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public void UndocumentedShaderRegister192_IsAcceptedFromTablesAndPackets()
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{
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var banks = NewBanks();
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var vertex = banks.Shader.Vertex.Copy();
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RegisterWriteTable.WriteShaderEntry(banks, SpiShaderUndocumented192, 1, PacketAddress);
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Assert.Equal(1u, WriteShader(banks, SpiShaderUndocumented192, 1));
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Assert.Equal(vertex.LocalAddress, banks.Shader.Vertex.LocalAddress);
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Assert.Equal(vertex.HullAddress, banks.Shader.Vertex.HullAddress);
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}
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[Fact]
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public void UndocumentedUserConfigRegister191_IsAcceptedFromTablesAndPackets()
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{
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var banks = NewBanks();
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var primitiveType = banks.UserConfig.PrimitiveType;
|
||||
RegisterWriteTable.WriteUserConfigEntry(banks, UserConfigUndocumented191, 0, PacketAddress);
|
||||
Assert.Equal(1u, WriteUserConfig(banks, UserConfigUndocumented191, 0));
|
||||
Assert.Equal(primitiveType, banks.UserConfig.PrimitiveType);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void CapturedMixedSampleRegistersKeepDepthStorageSeparateFromEqaaAnchors()
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue