[spirvtranslator] Added V_CMPX_NE_U64 instruction
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@ -1783,8 +1783,14 @@ public static partial class Gen5SpirvTranslator
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}
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else if (opcode is not ("VCmpClassF32" or "VCmpxClassF32"))
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{
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var left = GetRawSource(instruction, 0);
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var right = GetRawSource(instruction, 1);
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var compare64 = opcode.EndsWith("U64", StringComparison.Ordinal) ||
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opcode.EndsWith("I64", StringComparison.Ordinal);
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var left = compare64
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? GetRawSource64(instruction, 0)
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: GetRawSource(instruction, 0);
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var right = compare64
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? GetRawSource64(instruction, 1)
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: GetRawSource(instruction, 1);
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var signed = opcode.EndsWith("I32", StringComparison.Ordinal);
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if (signed)
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{
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@ -1798,6 +1804,7 @@ public static partial class Gen5SpirvTranslator
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"VCmpEqU32" or "VCmpxEqU32" => SpirvOp.IEqual,
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"VCmpNeI32" or "VCmpxNeI32" or
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"VCmpNeU32" or "VCmpxNeU32" => SpirvOp.INotEqual,
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"VCmpxNeU64" => SpirvOp.INotEqual,
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"VCmpLtI32" or "VCmpxLtI32" => SpirvOp.SLessThan,
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"VCmpLeI32" or "VCmpxLeI32" => SpirvOp.SLessThanEqual,
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"VCmpGtI32" or "VCmpxGtI32" => SpirvOp.SGreaterThan,
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@ -1010,6 +1010,7 @@ public static partial class Gen5ShaderTranslator
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0xED => "VCmpNeqF16",
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0xEE => "VCmpNltF16",
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0xEF => "VCmpTruF16",
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0xF5 => "VCmpxNeU64",
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0xF8 => "VCmpxUF16",
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0xF9 => "VCmpxNgeF16",
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0xFA => "VCmpxNlgF16",
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@ -143,6 +143,20 @@ public sealed class Gen5ShaderAtomicDecodeTests
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Assert.False(control.Gds);
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}
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[Fact]
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public void VCmpxNeU64_DecodesVectorRegisterPairs()
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{
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// V_CMPX_NE_U64 v[0:1], v[3:4]. The translator consumes each encoded
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// source as the low register of a 64-bit pair and updates EXEC.
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var instruction = DecodeSingle(0x7DEA0700);
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Assert.Equal("VCmpxNeU64", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(3) },
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instruction.Sources);
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Assert.Empty(instruction.Destinations);
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}
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private static Gen5ShaderInstruction DecodeSingle(params uint[] words)
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{
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var memory = new FakeCpuMemory(ShaderAddress, 0x1000);
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