345 lines
13 KiB
C#
345 lines
13 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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// Decodes synthetic GFX10 atomic instructions and checks the opcode names and operand wiring
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// that the SPIR-V translator relies on. Word layouts follow the RDNA2 ISA manual:
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// MUBUF op=word0[24:18], MIMG op=word0[24:18], DS op=word0[25:18].
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public sealed class Gen5ShaderAtomicDecodeTests
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{
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private const ulong ShaderAddress = 0x1_0000_0000;
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private const uint EndPgm = 0xBF810000;
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[Fact]
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public void BufferAtomicUmax_DecodesControlAndDestination()
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{
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// BUFFER_ATOMIC_UMAX v1, off, s[0:3], 128 offset:8 glc
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var instruction = DecodeSingle(0xE0E04008, 0x80000100);
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Assert.Equal("BufferAtomicUmax", instruction.Opcode);
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var control = Assert.IsType<Gen5BufferMemoryControl>(instruction.Control);
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Assert.Equal(1u, control.DwordCount);
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Assert.Equal(1u, control.VectorData);
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Assert.Equal(0u, control.ScalarResource);
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Assert.Equal(8, control.OffsetBytes);
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Assert.True(control.Glc);
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Assert.Equal(new[] { Gen5Operand.Vector(1) }, instruction.Destinations);
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}
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[Fact]
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public void BufferAtomicCmpswap_UsesTwoDataRegisters()
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{
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// BUFFER_ATOMIC_CMPSWAP v[1:2], off, s[0:3], 128 glc
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var instruction = DecodeSingle(0xE0C44000, 0x80000100);
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Assert.Equal("BufferAtomicCmpswap", instruction.Opcode);
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var control = Assert.IsType<Gen5BufferMemoryControl>(instruction.Control);
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Assert.Equal(2u, control.DwordCount);
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Assert.Equal(1u, control.VectorData);
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}
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[Theory]
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[InlineData(0xE0FC4000u, "BufferAtomicFmin")]
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[InlineData(0xE1004000u, "BufferAtomicFmax")]
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public void BufferAtomicFloatMinMax_Decode(uint word, string opcode)
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{
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var instruction = DecodeSingle(word, 0x80000100);
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Assert.Equal(opcode, instruction.Opcode);
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var control = Assert.IsType<Gen5BufferMemoryControl>(instruction.Control);
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Assert.Equal(1u, control.DwordCount);
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Assert.Equal(1u, control.VectorData);
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Assert.Equal(0u, control.ScalarResource);
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}
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[Fact]
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public void BufferAtomicOrX2_UsesTwoDataRegisters()
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{
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// BUFFER_ATOMIC_OR_X2 v[1:2], off, s[0:3], 128 glc
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var instruction = DecodeSingle(0xE1684000, 0x80000100);
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Assert.Equal("BufferAtomicOrX2", instruction.Opcode);
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var control = Assert.IsType<Gen5BufferMemoryControl>(instruction.Control);
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Assert.Equal(2u, control.DwordCount);
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Assert.Equal(1u, control.VectorData);
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Assert.Equal(
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new[] { Gen5Operand.Vector(1), Gen5Operand.Vector(2) },
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instruction.Destinations);
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}
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[Fact]
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public void BufferAtomicSwapX2_UsesTwoDataRegisters()
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{
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// BUFFER_ATOMIC_SWAP_X2 v[1:2], off, s[0:3], 128 glc
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var instruction = DecodeSingle(0xE1404000, 0x80000100);
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Assert.Equal("BufferAtomicSwapX2", instruction.Opcode);
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var control = Assert.IsType<Gen5BufferMemoryControl>(instruction.Control);
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Assert.Equal(2u, control.DwordCount);
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Assert.Equal(1u, control.VectorData);
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Assert.Equal(new[] { Gen5Operand.Vector(1), Gen5Operand.Vector(2) }, instruction.Destinations);
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}
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[Fact]
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public void ImageAtomicAdd_KeepsDataRegisterAsDestination()
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{
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// IMAGE_ATOMIC_ADD v2, v[0:1], s[4:11] dmask:0x1 dim:2D glc
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var instruction = DecodeSingle(0xF0442100, 0x00010200);
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Assert.Equal("ImageAtomicAdd", instruction.Opcode);
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var control = Assert.IsType<Gen5ImageControl>(instruction.Control);
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Assert.Equal(2u, control.VectorData);
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Assert.Equal(4u, control.ScalarResource);
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Assert.True(control.Glc);
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Assert.Equal(new[] { Gen5Operand.Vector(2) }, instruction.Destinations);
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}
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[Fact]
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public void ImageBvhIntersectRay_UsesOpcodeBitSevenFromOpm()
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{
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// IMAGE_BVH_INTERSECT_RAY v[12:15], v[0:10], s[4:7] (op 0xE6: word0[24:18]=0x66, OPM=1)
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var instruction = DecodeSingle(0xF1980F01, 0x00010C00);
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Assert.Equal("ImageBvhIntersectRay", instruction.Opcode);
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var control = Assert.IsType<Gen5RayIntersectControl>(instruction.Control);
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Assert.Equal(12u, control.VectorData);
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Assert.Equal(4u, control.ScalarResource);
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Assert.Equal(
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Enumerable.Range(12, 4).Select(index => Gen5Operand.Vector((uint)index)),
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instruction.Destinations);
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Assert.Equal(
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Enumerable.Range(0, 11).Select(index => Gen5Operand.Vector((uint)index)).Append(Gen5Operand.Scalar(4)),
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instruction.Sources);
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}
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[Fact]
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public void DsAppend_ReadsTheGdsBitAtBit17()
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{
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// DS_APPEND v0 offset:16 gds (Astro Bot's indirect-dispatch producer)
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var instruction = DecodeSingle(0xD8FA0010, 0x00000000);
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Assert.Equal("DsAppend", instruction.Opcode);
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var control = Assert.IsType<Gen5DataShareControl>(instruction.Control);
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Assert.True(control.Gds);
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Assert.Equal(16u, control.SingleOffsetBytes);
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}
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[Fact]
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public void Vop3CompareGtU64_WritesTheScalarPairInVdst()
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{
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// V_CMP_GT_U64 s[4:5], v[0:1], v[2:3] (VOP3 op 0x0E4)
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var instruction = DecodeSingle(0xD4E40004, 0x00020500);
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Assert.Equal("VCmpGtU64", instruction.Opcode);
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var control = Assert.IsType<Gen5Vop3Control>(instruction.Control);
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Assert.Equal(4u, control.ScalarDestination);
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Assert.Equal(new[] { Gen5Operand.Scalar(4) }, instruction.Destinations);
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Assert.Equal(new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(2) }, instruction.Sources);
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}
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[Fact]
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public void SSetprio_Decodes()
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{
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// S_SETPRIO 3 (SOPP op 0x0F)
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var instruction = DecodeSingle(0xBF8F0003);
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Assert.Equal("SSetprio", instruction.Opcode);
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}
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[Fact]
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public void DsAddU32_HasAddressAndDataSourcesButNoDestination()
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{
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// DS_ADD_U32 v0, v1
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var instruction = DecodeSingle(0xD8000000, 0x00000100);
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Assert.Equal("DsAddU32", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(1) },
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instruction.Sources);
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Assert.Empty(instruction.Destinations);
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}
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[Fact]
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public void DsAddRtnU32_WritesReturnRegister()
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{
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// DS_ADD_RTN_U32 v3, v0, v1
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var instruction = DecodeSingle(0xD8800000, 0x03000100);
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Assert.Equal("DsAddRtnU32", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(1) },
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instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(3) }, instruction.Destinations);
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}
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[Theory]
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[InlineData(0xD8480004u, "DsMinF32")]
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[InlineData(0xD84C0008u, "DsMaxF32")]
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public void DsFloatMinMax_KeepReplacementAndCompareOperands(uint word, string opcode)
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{
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// DATA0 is the replacement value and DATA1 is the float compare operand.
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var instruction = DecodeSingle(word, 0x00010907);
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Assert.Equal(opcode, instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(7), Gen5Operand.Vector(9), Gen5Operand.Vector(1) },
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instruction.Sources);
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Assert.Empty(instruction.Destinations);
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}
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[Fact]
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public void DsCmpstRtnB32_OrdersComparatorBeforeNewValue()
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{
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// DS_CMPST_RTN_B32 v3, v0, v1, v2 - DATA0 (v1) is the comparator, DATA1 (v2) the
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// new value, reversed relative to buffer/image cmpswap.
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var instruction = DecodeSingle(0xD8C00000, 0x03020100);
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Assert.Equal("DsCmpstRtnB32", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(1), Gen5Operand.Vector(2) },
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instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(3) }, instruction.Destinations);
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}
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[Fact]
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public void DsWriteB32_CombinesBothOffsetBytes()
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{
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// DS_WRITE_B32 v0, v1 offset:0x0808.
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var instruction = DecodeSingle(0xD8340808, 0x00000100);
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Assert.Equal("DsWriteB32", instruction.Opcode);
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var control = Assert.IsType<Gen5DataShareControl>(instruction.Control);
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Assert.Equal(0x08u, control.Offset0);
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Assert.Equal(0x08u, control.Offset1);
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Assert.Equal(0x0808u, control.SingleOffsetBytes);
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}
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[Fact]
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public void DsReadI8_DecodesAddressAndDestination()
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{
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// DS_READ_I8 v5, v7 offset:3
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var instruction = DecodeSingle(0xD8E40003, 0x05000007);
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Assert.Equal("DsReadI8", instruction.Opcode);
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Assert.Equal(new[] { Gen5Operand.Vector(7) }, instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(5) }, instruction.Destinations);
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var control = Assert.IsType<Gen5DataShareControl>(instruction.Control);
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Assert.Equal(3u, control.SingleOffsetBytes);
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}
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[Theory]
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[InlineData(0xD8F83412u, "DsAppend")]
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[InlineData(0xD8F43412u, "DsConsume")]
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public void DsWaveCounter_UsesM0AndReturnsOldValue(uint word, string opcode)
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{
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var instruction = DecodeSingle(word, 0x07000000);
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Assert.Equal(opcode, instruction.Opcode);
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Assert.Equal(new[] { Gen5Operand.Scalar(124) }, instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(7) }, instruction.Destinations);
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var control = Assert.IsType<Gen5DataShareControl>(instruction.Control);
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Assert.Equal(0x12u, control.Offset0);
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Assert.Equal(0x34u, control.Offset1);
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Assert.Equal(0x3412u, control.SingleOffsetBytes);
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Assert.False(control.Gds);
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}
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[Fact]
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public void VCmpxNeU64_DecodesVectorRegisterPairs()
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{
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// V_CMPX_NE_U64 v[0:1], v[3:4]. The translator consumes each encoded
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// source as the low register of a 64-bit pair and updates EXEC.
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var instruction = DecodeSingle(0x7DEA0700);
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Assert.Equal("VCmpxNeU64", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(3) },
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instruction.Sources);
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Assert.Empty(instruction.Destinations);
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}
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[Fact]
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public void VCmpNeU64_DecodesVectorRegisterPairs()
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{
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// V_CMP_NE_U64 v[0:1], v[3:4].
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var instruction = DecodeSingle(0x7DCA0700);
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Assert.Equal("VCmpNeU64", instruction.Opcode);
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Assert.Equal(
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new[] { Gen5Operand.Vector(0), Gen5Operand.Vector(3) },
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instruction.Sources);
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Assert.Empty(instruction.Destinations);
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}
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[Fact]
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public void VFfbhU32_DecodesVop1Opcode39()
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{
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// V_FFBH_U32 v1, v2.
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var instruction = DecodeSingle(0x7E027302);
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Assert.Equal("VFfbhU32", instruction.Opcode);
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Assert.Equal(new[] { Gen5Operand.Vector(2) }, instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(1) }, instruction.Destinations);
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}
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[Fact]
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public void VCmpxClassF32_DecodesVopcOpcode98()
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{
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var instruction = DecodeSingle(0x7D300702);
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Assert.Equal("VCmpxClassF32", instruction.Opcode);
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}
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[Fact]
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public void VAlignbitB32_DecodesVop3Opcode14E()
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{
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var instruction = DecodeSingle(0xD14E0001, 0x040E0502);
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Assert.Equal("VAlignbitB32", instruction.Opcode);
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Assert.Equal(new[] { Gen5Operand.Vector(2), Gen5Operand.Vector(2), Gen5Operand.Vector(3) }, instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(1) }, instruction.Destinations);
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}
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[Fact]
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public void VAlignbyteB32_DecodesVop3Opcode14F()
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{
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var instruction = DecodeSingle(0xD14F0001, 0x040E0502);
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Assert.Equal("VAlignbyteB32", instruction.Opcode);
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Assert.Equal(new[] { Gen5Operand.Vector(2), Gen5Operand.Vector(2), Gen5Operand.Vector(3) }, instruction.Sources);
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Assert.Equal(new[] { Gen5Operand.Vector(1) }, instruction.Destinations);
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}
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private static Gen5ShaderInstruction DecodeSingle(params uint[] words)
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{
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var memory = new FakeCpuMemory(ShaderAddress, 0x1000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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WriteProgram(memory, ShaderAddress, words);
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Assert.True(
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Gen5ShaderTranslator.TryDecodeProgram(
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ctx,
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ShaderAddress,
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out var program,
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out var error),
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error);
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return program.Instructions[0];
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}
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internal static void WriteProgram(FakeCpuMemory memory, ulong address, uint[] words)
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{
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Span<byte> buffer = stackalloc byte[4];
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foreach (var word in words.Append(EndPgm))
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{
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BinaryPrimitives.WriteUInt32LittleEndian(buffer, word);
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Assert.True(memory.TryWrite(address, buffer));
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address += sizeof(uint);
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}
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}
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}
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