251 lines
9.5 KiB
C#
251 lines
9.5 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using System.Text;
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using SharpEmu.ShaderCompiler.Vulkan;
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using Xunit;
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using static SharpEmu.ShaderCompiler.Tests.Resources.ResourceTestProgram;
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namespace SharpEmu.ShaderCompiler.Tests;
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// Checks the SPIR-V each wave lowering (NativeWave32, NativeWave64, EmulatedWave64) produces for the
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// same guest programs: which subgroup instructions appear, how a ballot is split into a 64-bit mask,
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// and whether the workgroup exchange / rendezvous machinery exists.
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public sealed class Gen5WaveLoweringTests
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{
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public enum Lowering { Wave32, NativeWave64, EmulatedWave64 }
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private sealed record Module(
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IReadOnlyList<(SpirvOp Op, uint[] Operands)> Instructions,
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IReadOnlyList<string> Names)
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{
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public int Count(SpirvOp op) => Instructions.Count(instruction => instruction.Op == op);
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// CompositeExtract of a ballot result: its literal index is the last operand.
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public IReadOnlyList<uint> BallotExtractIndices()
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{
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var ballots = Instructions.Where(i => i.Op == SpirvOp.GroupNonUniformBallot).Select(i => i.Operands[1]).ToHashSet();
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return Instructions
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.Where(i => i.Op == SpirvOp.CompositeExtract && ballots.Contains(i.Operands[2]))
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.Select(i => i.Operands[^1])
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.ToList();
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}
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}
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private static Module Parse(byte[] spirv)
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{
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var instructions = new List<(SpirvOp, uint[])>();
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var names = new List<string>();
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for (var offset = 20; offset < spirv.Length;)
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{
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var word = BinaryPrimitives.ReadUInt32LittleEndian(spirv.AsSpan(offset));
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var length = (int)(word >> 16);
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var op = (SpirvOp)(word & 0xFFFF);
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var operands = new uint[length - 1];
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for (var index = 0; index < operands.Length; index++)
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{
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operands[index] = BinaryPrimitives.ReadUInt32LittleEndian(spirv.AsSpan(offset + 4 + index * 4));
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}
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instructions.Add((op, operands));
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if (op == SpirvOp.Name)
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{
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var text = new List<byte>();
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for (var index = 1; index < operands.Length; index++)
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{
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text.AddRange(BitConverter.GetBytes(operands[index]));
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}
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names.Add(Encoding.UTF8.GetString(text.ToArray()).TrimEnd('\0'));
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}
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offset += length * 4;
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}
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return new Module(instructions, names);
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}
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private static Module Compile(Gen5ShaderProgram program, Lowering lowering, uint threads = 64)
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{
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var (plan, resources, layout) = Prepare(program);
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var configured = new ShaderCompileRequest(plan, resources, layout)
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{
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WaveSize = lowering == Lowering.Wave32 ? 32u : 64u,
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HostWave64Supported = lowering == Lowering.NativeWave64,
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LocalSizeX = threads,
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};
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Assert.True(Gen5SpirvTranslator.TryCompileProgram(configured, out var shader, out var error), error);
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return Parse(shader.Spirv);
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}
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// v_cmp_lt_u32 vcc, v0, v1 : a per-lane compare whose result becomes a wave mask.
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private static Gen5ShaderProgram CompareProgram() => Program(
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Vopc(0, "VCmpLtU32", Operand(5), 1),
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EndProgram(4));
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private static Gen5ShaderProgram ReadFirstLaneProgram() => Program(
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ReadFirstLane(0, 4, 0),
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EndProgram(4));
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private static Gen5ShaderProgram ReadLaneProgram(uint lane) => Program(
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ReadLane(0, 4, 0, lane),
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EndProgram(4));
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private static Gen5ShaderProgram DataShareProgram(bool barrierBetween) =>
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Program(
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new[]
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{
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DataShare(0, "DsWriteB32", false, [Gen5Operand.Vector(0), Gen5Operand.Vector(1)], [], 0, 0),
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}
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.Concat(barrierBetween
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? new[] { new Gen5ShaderInstruction(4, Gen5ShaderEncoding.Sopp, "SBarrier", [0u], [], [], null) }
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: [])
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.Concat(new[]
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{
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DataShare(8, "DsReadB32", false, [Gen5Operand.Vector(0)], [2u], 0, 0),
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EndProgram(16),
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})
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.ToArray());
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[Theory]
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[InlineData(Lowering.Wave32)]
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[InlineData(Lowering.NativeWave64)]
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[InlineData(Lowering.EmulatedWave64)]
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public void EveryLoweringCompilesTheBasicWavePrograms(Lowering lowering)
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{
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foreach (var program in new[] { CompareProgram(), ReadFirstLaneProgram(), ReadLaneProgram(0), ReadLaneProgram(33), DataShareProgram(false), DataShareProgram(true) })
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{
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Compile(program, lowering);
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}
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}
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[Fact]
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public void Wave32_BallotUsesOnlyTheLowWord()
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{
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var module = Compile(CompareProgram(), Lowering.Wave32);
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Assert.True(module.Count(SpirvOp.GroupNonUniformBallot) > 0);
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Assert.All(module.BallotExtractIndices(), index => Assert.Equal(0u, index));
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}
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[Fact]
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public void NativeWave64_BallotCombinesBothWords()
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{
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var module = Compile(CompareProgram(), Lowering.NativeWave64);
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var indices = module.BallotExtractIndices();
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Assert.Contains(0u, indices);
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Assert.Contains(1u, indices);
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}
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[Fact]
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public void OnlyTheEmulatedLoweringDeclaresTheExchange()
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{
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foreach (var lowering in new[] { Lowering.Wave32, Lowering.NativeWave64 })
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{
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var module = Compile(ReadFirstLaneProgram(), lowering);
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Assert.DoesNotContain("wave64Exchange", module.Names);
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Assert.DoesNotContain("wave64ExchangeParity", module.Names);
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}
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var emulated = Compile(ReadFirstLaneProgram(), Lowering.EmulatedWave64);
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Assert.Contains("wave64ExchangeParity", emulated.Names);
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Assert.Contains("wave64Exchange", emulated.Names);
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}
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[Fact]
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public void EmulatedWave64_NeedsNoExchangeWithoutSubgroupOperations()
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{
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var module = Compile(Program(Vop2(0, "VAddI32", 1, Operand(1), Gen5Operand.Vector(0)), EndProgram(4)), Lowering.EmulatedWave64);
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Assert.DoesNotContain("wave64ExchangeParity", module.Names);
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}
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[Theory]
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[InlineData(Lowering.Wave32, 64u)]
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[InlineData(Lowering.NativeWave64, 64u)]
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[InlineData(Lowering.NativeWave64, 256u)]
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public void NativeLoweringsAddNoBarriersAroundSharedMemory(Lowering lowering, uint threads)
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{
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var module = Compile(DataShareProgram(false), lowering, threads);
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Assert.Equal(0, module.Count(SpirvOp.ControlBarrier));
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}
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[Theory]
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[InlineData(false, 2)]
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[InlineData(true, 2)]
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public void EmulatedWave64_OrdersSharedMemoryPhasesWithinOneWave(bool explicitBarrier, int expectedBarriers)
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{
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var module = Compile(DataShareProgram(explicitBarrier), Lowering.EmulatedWave64, threads: 64);
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Assert.Equal(expectedBarriers, module.Count(SpirvOp.ControlBarrier));
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}
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[Fact]
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public void EmulatedWave64_MultiWaveGroupsUseNoWorkgroupBarrierForSharedMemoryPhases()
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{
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var module = Compile(DataShareProgram(false), Lowering.EmulatedWave64, threads: 128);
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Assert.Equal(0, module.Count(SpirvOp.ControlBarrier));
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}
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[Fact]
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public void EmulatedWave64_MultiWaveExchangeMeetsAtAnArrivalCounter()
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{
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var single = Compile(ReadFirstLaneProgram(), Lowering.EmulatedWave64, threads: 64);
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var multi = Compile(ReadFirstLaneProgram(), Lowering.EmulatedWave64, threads: 256);
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Assert.DoesNotContain("wave64RendezvousEpoch", single.Names);
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Assert.Contains("wave64RendezvousEpoch", multi.Names);
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Assert.True(multi.Count(SpirvOp.AtomicIAdd) > single.Count(SpirvOp.AtomicIAdd));
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}
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[Theory]
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[InlineData(Lowering.Wave32)]
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[InlineData(Lowering.NativeWave64)]
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public void NativeLoweringsNeverDeclareARendezvous(Lowering lowering)
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{
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var module = Compile(ReadFirstLaneProgram(), lowering, threads: 256);
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Assert.DoesNotContain("wave64RendezvousEpoch", module.Names);
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Assert.Equal(0, module.Count(SpirvOp.AtomicIAdd));
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}
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[Fact]
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public void HostWave64SupportDoesNotChangeAWave32Shader()
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{
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var program = ReadFirstLaneProgram();
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var (plan, resources, layout) = Prepare(program);
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byte[] Compile32(bool hostWave64)
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{
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var configured = new ShaderCompileRequest(plan, resources, layout)
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{
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WaveSize = 32,
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HostWave64Supported = hostWave64,
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LocalSizeX = 64,
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};
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Assert.True(Gen5SpirvTranslator.TryCompileProgram(configured, out var shader, out var error), error);
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return shader.Spirv.ToArray();
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}
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Assert.Equal(Compile32(false), Compile32(true));
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}
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[Theory]
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[InlineData(Lowering.Wave32)]
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[InlineData(Lowering.NativeWave64)]
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[InlineData(Lowering.EmulatedWave64)]
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public void ReadLaneBroadcastsFromTheRequestedLane(Lowering lowering)
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{
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var module = Compile(ReadLaneProgram(33), lowering);
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Assert.True(
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module.Count(SpirvOp.GroupNonUniformBroadcast) > 0 || module.Count(SpirvOp.GroupNonUniformShuffle) > 0 ||
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module.Count(SpirvOp.Store) > 0);
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}
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[Theory]
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[InlineData(Lowering.Wave32)]
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[InlineData(Lowering.NativeWave64)]
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[InlineData(Lowering.EmulatedWave64)]
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public void LoweringsAreDeterministic(Lowering lowering)
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{
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var first = Compile(CompareProgram(), lowering);
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var second = Compile(CompareProgram(), lowering);
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Assert.Equal(first.Instructions.Count, second.Instructions.Count);
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}
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}
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