209 lines
9.8 KiB
C#
209 lines
9.8 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.VideoOut;
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using Xunit;
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namespace SharpEmu.Libs.Tests.VideoOut;
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public sealed class VideoOutOutputSupportTests
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{
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private const string OpenNid = "Up36PTk687E";
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private const string CloseNid = "uquVH4-Du78";
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private const string OutputSupportNid = "Nv8c-Kb+DUM";
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private const string OutputStatusNid = "utPrVdxio-8";
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private const string ConfigureOutputNid = "w0hLuNarQxY";
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private const ulong MemoryBase = 0x1_0000_0000;
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private const ulong OptionsAddress = MemoryBase + 0x100;
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private static readonly ulong InvalidValue = unchecked((ulong)(int)0x80290001);
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private static readonly ulong InvalidHandle = unchecked((ulong)(int)0x8029000B);
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private static readonly ulong UnsupportedOutputMode = unchecked((ulong)(int)0x80290016);
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private static readonly ulong InvalidOption = unchecked((ulong)(int)0x8029001A);
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private static readonly ulong MemoryFault =
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unchecked((ulong)(int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT);
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[Theory]
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[InlineData(HostHdrMode.Auto, false, true, false)]
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[InlineData(HostHdrMode.Auto, true, false, false)]
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[InlineData(HostHdrMode.Auto, true, true, true)]
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[InlineData(HostHdrMode.On, false, true, true)]
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[InlineData(HostHdrMode.On, true, true, true)]
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[InlineData(HostHdrMode.On, true, false, false)]
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[InlineData(HostHdrMode.Off, true, true, false)]
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public void OutputStatusReportsHdrOnlyWhenAllowedAndSupported(
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HostHdrMode mode, bool displayHdrEnabled, bool surfaceSupportsHdr, bool expectedHdr)
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{
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var supported = new HostVideoOptions { HdrMode = mode }.CanUseHdr(displayHdrEnabled, surfaceSupportsHdr);
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Assert.Equal(expectedHdr, supported);
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var bytes = Enumerable.Repeat((byte)0xA5, 0x32).ToArray();
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VideoOutExports.WriteOutputStatus(bytes.AsSpan(1, 0x30), 3840, 2160, 120, supported);
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Assert.Equal(0xA5, bytes[0]);
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Assert.Equal(0xA5, bytes[^1]);
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var status = bytes.AsSpan(1, 0x30);
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Assert.Equal(2U, BinaryPrimitives.ReadUInt32LittleEndian(status));
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Assert.Equal(expectedHdr ? 2U : 1U, BinaryPrimitives.ReadUInt32LittleEndian(status[4..]));
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Assert.Equal(13UL, BinaryPrimitives.ReadUInt64LittleEndian(status[8..]));
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Assert.Equal(expectedHdr ? 1UL : 0UL, BinaryPrimitives.ReadUInt64LittleEndian(status[0x10..]));
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Assert.All(status[0x18..].ToArray(), value => Assert.Equal(0, value));
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}
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[Theory]
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[InlineData(Generation.Gen4)]
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[InlineData(Generation.Gen5)]
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public void OutputStatusUsesRefreshRateCodeAndPreservesBufferBoundaries(Generation generation)
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{
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var manager = new ModuleManager();
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manager.RegisterExports(SharpEmu.Generated.SysAbiExportRegistry.CreateExports(generation));
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var memory = new FakeCpuMemory(MemoryBase, 0x1000);
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var context = new CpuContext(memory, generation);
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Assert.True(manager.TryDispatch(OpenNid, context, out _));
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var handle = context[CpuRegister.Rax];
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Assert.InRange(handle, 1UL, (ulong)int.MaxValue);
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try
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{
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var buffer = Enumerable.Repeat((byte)0xA5, 0x32).ToArray();
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Assert.True(memory.TryWrite(OptionsAddress, buffer));
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context[CpuRegister.Rdi] = handle;
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context[CpuRegister.Rsi] = OptionsAddress + 1;
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Assert.True(manager.TryDispatch(OutputStatusNid, context, out _));
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Assert.Equal(0UL, context[CpuRegister.Rax]);
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Assert.True(memory.TryRead(OptionsAddress, buffer));
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var expected = new byte[0x32];
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expected[0] = 0xA5;
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expected[^1] = 0xA5;
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BinaryPrimitives.WriteUInt32LittleEndian(expected.AsSpan(1), 1);
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BinaryPrimitives.WriteUInt32LittleEndian(expected.AsSpan(5), 1);
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BinaryPrimitives.WriteUInt64LittleEndian(expected.AsSpan(9), 3);
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Assert.Equal(expected, buffer);
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context[CpuRegister.Rsi] = 0;
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Assert.True(manager.TryDispatch(OutputStatusNid, context, out _));
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Assert.Equal(unchecked((ulong)(int)0x80290002), context[CpuRegister.Rax]);
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context[CpuRegister.Rsi] = MemoryBase + 0xFF0;
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Assert.True(manager.TryDispatch(OutputStatusNid, context, out _));
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Assert.Equal(MemoryFault, context[CpuRegister.Rax]);
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context[CpuRegister.Rsi] = OptionsAddress + 1;
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context[CpuRegister.Rdi] = ulong.MaxValue;
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Assert.True(manager.TryDispatch(OutputStatusNid, context, out _));
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Assert.Equal(InvalidHandle, context[CpuRegister.Rax]);
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}
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finally
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{
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context[CpuRegister.Rdi] = handle;
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Assert.True(manager.TryDispatch(CloseNid, context, out _));
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}
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}
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[Fact]
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public void Gen5QueryReportsCapabilitiesAndValidatesArguments()
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{
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var gen4Manager = new ModuleManager();
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gen4Manager.RegisterExports(
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SharpEmu.Generated.SysAbiExportRegistry.CreateExports(Generation.Gen4));
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Assert.False(gen4Manager.TryGetExport(OutputSupportNid, out _));
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var manager = new ModuleManager();
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manager.RegisterExports(
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SharpEmu.Generated.SysAbiExportRegistry.CreateExports(Generation.Gen5));
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Assert.True(manager.TryGetExport(OutputSupportNid, out var export));
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Assert.Equal("sceVideoOutIsOutputSupported", export.Name);
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Assert.Equal("libSceVideoOut", export.LibraryName);
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Assert.Equal(Generation.Gen5, export.Target);
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var memory = new FakeCpuMemory(MemoryBase, 0x1000);
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var context = new CpuContext(memory, Generation.Gen5);
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context[CpuRegister.Rdi] = 0;
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context[CpuRegister.Rsi] = 0;
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context[CpuRegister.Rdx] = 0;
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context[CpuRegister.Rcx] = 0;
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Assert.True(manager.TryDispatch(OpenNid, context, out _));
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var handle = context[CpuRegister.Rax];
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Assert.NotEqual(0UL, handle);
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try
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{
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Assert.Equal(1UL, DispatchOutputSupport(manager, context, handle, 1));
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Assert.Equal(0UL, DispatchOutputSupport(manager, context, handle, 15));
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Assert.Equal(
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InvalidHandle,
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DispatchOutputSupport(manager, context, ulong.MaxValue, 1));
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Assert.Equal(
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InvalidValue,
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DispatchOutputSupport(manager, context, handle, 1, reservedPointer: 1));
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Assert.Equal(
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InvalidValue,
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DispatchOutputSupport(manager, context, handle, 1, reserved: 1));
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Assert.Equal(
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1UL,
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DispatchOutputSupport(manager, context, handle, 1, OptionsAddress));
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Assert.Equal(
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MemoryFault,
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DispatchOutputSupport(manager, context, handle, 1, MemoryBase + 0x1000));
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Assert.True(memory.TryWrite(OptionsAddress, new byte[] { 1 }));
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Assert.Equal(
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InvalidOption,
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DispatchOutputSupport(manager, context, handle, 1, OptionsAddress));
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Assert.Equal(
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UnsupportedOutputMode,
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DispatchOutputSupport(manager, context, handle, 2));
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// Configuration must use the same validation as the capability query.
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(UnsupportedOutputMode, context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, handle, 1, OptionsAddress);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(InvalidOption, context[CpuRegister.Rax]);
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Assert.True(memory.TryWrite(OptionsAddress, new byte[0x40]));
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DispatchOutputSupport(manager, context, handle, 1, OptionsAddress);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(0UL, context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, handle, 15);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(unchecked((ulong)(int)0x80290019), context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, handle, 1, reserved: 1);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(InvalidValue, context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, handle, 1, reservedPointer: 1);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(InvalidValue, context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, handle, 1, MemoryBase + 0x1000);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(MemoryFault, context[CpuRegister.Rax]);
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DispatchOutputSupport(manager, context, ulong.MaxValue, 1);
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Assert.True(manager.TryDispatch(ConfigureOutputNid, context, out _));
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Assert.Equal(InvalidHandle, context[CpuRegister.Rax]);
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}
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finally
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{
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context[CpuRegister.Rdi] = handle;
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_ = manager.TryDispatch(CloseNid, context, out _);
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}
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}
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private static ulong DispatchOutputSupport(
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ModuleManager manager,
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CpuContext context,
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ulong handle,
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ulong mode,
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ulong optionsAddress = 0,
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ulong reservedPointer = 0,
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ulong reserved = 0)
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{
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context[CpuRegister.Rdi] = handle;
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context[CpuRegister.Rsi] = mode;
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context[CpuRegister.Rdx] = optionsAddress;
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context[CpuRegister.Rcx] = reservedPointer;
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context[CpuRegister.R8] = reserved;
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context[CpuRegister.R9] = 0x1FC;
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Assert.True(manager.TryDispatch(OutputSupportNid, context, out _));
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return context[CpuRegister.Rax];
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}
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}
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