315 lines
13 KiB
C#
315 lines
13 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.Libs.Gpu.Buffers;
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using SharpEmu.Libs.Tests.Gpu.Images;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Resources;
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using SharpEmu.ShaderCompiler.Vulkan;
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using Xunit;
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using static SharpEmu.ShaderCompiler.Tests.Resources.ResourceTestProgram;
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namespace SharpEmu.Libs.Tests.Gpu.Vulkan;
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public sealed class Wave64HalfMaskDeviceTests(HeadlessVulkanFixture fixture) : IClassFixture<HeadlessVulkanFixture>
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{
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private const uint Vcc = 106;
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private const uint Exec = 126;
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private static readonly Gen5Operand AllLanes = Gen5Operand.Source(193);
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private readonly List<Gen5ShaderInstruction> _instructions = [];
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private uint _pc;
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private uint Add(Gen5ShaderInstruction instruction)
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{
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var pc = _pc;
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_instructions.Add(instruction with { Pc = pc });
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_pc += 8;
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return pc;
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}
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private void Point(uint branchPc, uint targetPc)
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{
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var index = _instructions.FindIndex(instruction => instruction.Pc == branchPc);
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var offset = (short)(((int)targetPc - (int)branchPc - 4) / 4);
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_instructions[index] = _instructions[index] with { Words = [unchecked((uint)(ushort)offset)] };
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}
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private void Lane()
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{
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Add(Vop2(0, "VLshlrevB32", 2, Operand(3), Gen5Operand.Vector(1)));
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Add(Vop2(0, "VAddI32", 2, Gen5Operand.Vector(0), Gen5Operand.Vector(2)));
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}
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private uint CompareTo(string opcode, uint destination, Gen5Operand left, Gen5Operand right) =>
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Add(new Gen5ShaderInstruction(0, Gen5ShaderEncoding.Vop3, opcode, [0u, 0u], [left, right], [Gen5Operand.Scalar(destination)],
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new Gen5Vop3Control(0, 0, 0, false, 0, destination)));
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private uint[] Run(uint localDataShareDwords = 0)
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{
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Add(Vop2(0, "VLshlrevB32", 5, Operand(2), Gen5Operand.Vector(2)));
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Add(BufferAccess(0, "BufferStoreDword", 4, vectorData: 4, offsetEnabled: true, vectorAddress: 5));
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Add(EndProgram(0));
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var (plan, resources, layout) = Prepare(Program([.. _instructions]));
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var request = new ShaderCompileRequest(plan, resources, layout)
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{
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LocalSizeX = 8, LocalSizeY = 8, ThreadCountX = 8, ThreadCountY = 8, WaveSize = 64,
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LocalDataShareDwords = localDataShareDwords,
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};
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Assert.True(Gen5SpirvTranslator.TryCompileProgram(request, out var shader, out var error), error);
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Assert.NotNull(fixture.Vulkan);
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using var harness = new ImageTestHarness(fixture.Vulkan);
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using var runner = new LayoutComputeRunner(harness, request, shader.Spirv);
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var output = runner.CreateBuffer(256);
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var registers = new uint[256];
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registers[6] = 256;
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harness.Run(() => runner.Dispatch(registers,
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new Dictionary<DescriptorBindingKind, GpuBuffer[]> { [DescriptorBindingKind.Buffers] = [output] }, 1));
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var bytes = runner.ReadBack(output, 0, 256);
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harness.AssertNoValidationMessages();
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var lanes = new uint[64];
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for (var lane = 0; lane < lanes.Length; lane++)
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{
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lanes[lane] = BinaryPrimitives.ReadUInt32LittleEndian(bytes.AsSpan(lane * sizeof(uint)));
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}
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return lanes;
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}
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[Fact]
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public void ExplicitCompareMask_IsCollectedAcrossTheWave()
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{
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if (!Ready()) return;
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Lane();
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CompareTo("VCmpGeU32", 10, Gen5Operand.Vector(2), Operand(3));
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Add(MoveVectorFromScalar(0, 4, 10));
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Assert.All(Run(), x => Assert.Equal(0xFFFF_FFF8u, x));
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}
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[Fact]
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public void InitialExecContainsEveryLane()
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{
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if (!Ready()) return;
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Lane();
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Add(MoveVectorFromScalar(0, 4, 126));
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Assert.All(Run(), x => Assert.Equal(uint.MaxValue, x));
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}
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private bool Ready() => GatePrerequisites.Ready(fixture.Vulkan, shaderInt64: true);
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[Fact]
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public void MasksAcrossTheHalfBoundary_StayExactPerLaneAndWhenCounted()
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{
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if (!Ready()) return;
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Lane();
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CompareTo("VCmpLtU32", 10, Gen5Operand.Vector(2), Operand(40));
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Add(Vop2(0, "VAndB32", 6, Operand(1), Gen5Operand.Vector(2)));
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Add(Vopc(0, "VCmpEqU32", Operand(1), 6));
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Add(Sop2(0, "SAndB64", 12, Gen5Operand.Scalar(10), Gen5Operand.Scalar(Vcc)));
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Add(Vop3(0, "VCndmaskB32", 4, Operand(0), Operand(1000), Gen5Operand.Scalar(12)));
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Add(Sop1(0, "SBcnt1I32B64", 14, Gen5Operand.Scalar(12)));
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Add(Vop2(0, "VAddU32", 4, Gen5Operand.Scalar(14), Gen5Operand.Vector(4)));
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var lanes = Run();
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for (uint lane = 0; lane < 64; lane++)
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{
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Assert.Equal((lane & 1) != 0 && lane < 40 ? 1020u : 20u, lanes[lane]);
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}
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}
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[Theory]
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[InlineData(48u, 77u)]
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[InlineData(8u, 77u)]
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[InlineData(64u, 5u)]
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public void AnExecBranch_IsDecidedForTheWholeWave(uint firstActiveLane, uint expected)
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{
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if (!Ready()) return;
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Lane();
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Add(MoveScalar(0, 20, 5));
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Add(Vopc(0, "VCmpxLeU32", Operand(firstActiveLane), 2));
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var skip = Add(Branch(0, "SCbranchExecz", 0));
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Add(MoveScalar(0, 20, 77));
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var join = Add(Sop1(0, "SMovB64", Exec, AllLanes));
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Point(skip, join);
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Add(MoveVectorFromScalar(0, 4, 20));
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Assert.All(Run(), value => Assert.Equal(expected, value));
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}
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[Theory]
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[InlineData(50u, 9u)]
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[InlineData(10u, 9u)]
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[InlineData(64u, 3u)]
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public void AMaskWhoseSccIsRead_CountsBothHalves(uint threshold, uint expected)
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{
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if (!Ready()) return;
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Lane();
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Add(MoveScalar(0, 20, 3));
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CompareTo("VCmpGeU32", 10, Gen5Operand.Vector(2), Operand(threshold));
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Add(Sop2(0, "SAndB64", 12, Gen5Operand.Scalar(10), Gen5Operand.Scalar(Exec)));
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var skip = Add(Branch(0, "SCbranchScc0", 0));
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Add(MoveScalar(0, 20, 9));
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var join = Add(MoveVectorFromScalar(0, 4, 20));
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Point(skip, join);
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Assert.All(Run(), value => Assert.Equal(expected, value));
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}
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[Theory]
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[InlineData(0u)]
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[InlineData(64u)]
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public void SharedMemoryWrittenByOneHalf_IsReadByTheOther(uint localDataShareDwords)
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{
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if (!Ready()) return;
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Lane();
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Add(Vop2(0, "VLshlrevB32", 3, Operand(1), Gen5Operand.Vector(2)));
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Add(Vop2(0, "VAddU32", 3, Gen5Operand.Vector(2), Gen5Operand.Vector(3)));
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Add(Vop2(0, "VLshlrevB32", 6, Operand(2), Gen5Operand.Vector(2)));
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Add(Vopc(0, "VCmpxGtU32", Operand(32), 2));
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Add(BufferAccess(0, "BufferLoadDword", 4, vectorData: 8, offsetEnabled: true, vectorAddress: 6));
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Add(Vop2(0, "VAddU32", 3, Gen5Operand.Vector(8), Gen5Operand.Vector(3)));
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Add(DataShare(0, "DsWriteB32", false, [Gen5Operand.Vector(6), Gen5Operand.Vector(3)], []));
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Add(Sop1(0, "SMovB64", Exec, AllLanes));
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Add(Vop2(0, "VAndB32", 7, Operand(31), Gen5Operand.Vector(2)));
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Add(Vop2(0, "VLshlrevB32", 7, Operand(2), Gen5Operand.Vector(7)));
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Add(DataShare(0, "DsReadB32", false, [Gen5Operand.Vector(7)], [4]));
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var lanes = Run(localDataShareDwords);
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for (uint lane = 0; lane < 64; lane++)
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{
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Assert.Equal((lane & 31) * 3, lanes[lane]);
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}
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}
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[Fact]
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public void AnExecLoop_RunsEveryLaneItsOwnCount()
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{
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if (!Ready()) return;
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Lane();
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Add(Vop2(0, "VAndB32", 3, Operand(7), Gen5Operand.Vector(2)));
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Add(Vop2(0, "VAddU32", 3, Operand(1), Gen5Operand.Vector(3)));
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Add(MoveVector(0, 4, 0));
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Add(Sop1(0, "SMovB64", 20, Gen5Operand.Scalar(Exec)));
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var header = Add(Vopc(0, "VCmpxGtU32", Gen5Operand.Vector(3), 4));
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var exit = Add(Branch(0, "SCbranchExecz", 0));
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Add(Vop2(0, "VAddU32", 4, Operand(1), Gen5Operand.Vector(4)));
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var back = Add(Branch(0, "SBranch", 0));
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var done = Add(Sop1(0, "SMovB64", Exec, Gen5Operand.Scalar(20)));
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Point(exit, done);
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Point(back, header);
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var lanes = Run();
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for (uint lane = 0; lane < 64; lane++)
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{
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Assert.Equal((lane & 7) + 1, lanes[lane]);
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}
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}
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[Theory]
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[InlineData(false)]
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[InlineData(true)]
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public void ASingleBlockLoop_GroupsBothWaveHalvesAndCanBeSkipped(bool skip)
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{
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if (!Ready()) return;
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Lane();
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Add(Vop2(0, "VAndB32", 3, Operand(3), Gen5Operand.Vector(2)));
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Add(MoveVector(0, 4, 0));
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Add(Sop1(0, "SMovB64", 20, Gen5Operand.Scalar(Exec)));
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uint? bypass = skip ? Add(Branch(0, "SBranch", 0)) : null;
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var header = Add(ReadFirstLane(0, 22, 3));
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Add(Vopc(0, "VCmpxEqU32", Gen5Operand.Scalar(22), 3));
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Add(Vop2(0, "VAddU32", 4, Operand(1), Gen5Operand.Vector(3)));
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Add(Sop2(0, "SAndn2B64", 20, Gen5Operand.Scalar(20), Gen5Operand.Scalar(Exec)));
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Add(Sop1(0, "SMovB64", Exec, Gen5Operand.Scalar(20)));
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var back = Add(Branch(0, "SCbranchScc1", 0));
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var done = Add(Sop1(0, "SMovB64", Exec, AllLanes));
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Point(back, header);
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if (bypass is { } branch) Point(branch, done);
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var lanes = Run();
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for (uint lane = 0; lane < 64; lane++)
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Assert.Equal(skip ? 0u : (lane & 3) + 1, lanes[lane]);
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}
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[Theory]
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[InlineData(40u, 140u)]
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[InlineData(3u, 103u)]
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[InlineData(64u, 100u)]
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public void ReadFirstLane_TakesTheFirstActiveLaneOfTheWholeWave(uint firstActiveLane, uint expected)
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{
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if (!Ready()) return;
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Lane();
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Add(Vop2(0, "VAddU32", 3, Operand(100), Gen5Operand.Vector(2)));
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Add(Vopc(0, "VCmpxLeU32", Operand(firstActiveLane), 2));
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Add(ReadFirstLane(0, 20, 3));
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Add(Sop1(0, "SMovB64", Exec, AllLanes));
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Add(MoveVectorFromScalar(0, 4, 20));
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Assert.All(Run(), value => Assert.Equal(expected, value));
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}
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[Fact]
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public void ADemonsSoulsIndexRemap_CompilesOnTheDevice()
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{
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if (!Ready()) return;
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uint[] words =
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[
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0xBEFC03FFu, 0xA65CD91Eu, 0xBF960000u, 0xBFA00003u, 0xD7460002u, 0x04010C0Cu, 0xF4201A84u, 0xFA000000u,
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0xBF8CC07Fu, 0x7DA8046Au, 0xBF88002Au, 0xF4200304u, 0xFA000004u, 0xBF8CC07Fu, 0x7E000C0Cu, 0xBF070C80u,
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0x8588807Eu, 0x7E005700u, 0x100000FFu, 0x4F800000u, 0x7E060F00u, 0xD5766A00u, 0x0202060Cu, 0x7D8A0280u,
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0x4C020080u, 0x02000101u, 0xD56A0001u, 0x00020700u, 0x4C000303u, 0x4A020303u, 0x02000101u, 0xD56A0000u,
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0x00020500u, 0xD5690001u, 0x0002000Cu, 0x4C060302u, 0x7D8C02F9u, 0x06068A02u, 0x7D86060Cu, 0x87EA6A0Au,
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0x50000080u, 0xD5286A00u, 0x002A00C1u, 0xD5010000u, 0x002200C1u, 0xD5690000u, 0x0002000Cu, 0x4C000102u,
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0xE0002000u, 0x80000000u, 0xBF8C3F70u, 0xE0102000u, 0x80010002u, 0xBF810000u,
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];
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var bytes = new byte[words.Length * sizeof(uint)];
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for (var index = 0; index < words.Length; index++)
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BinaryPrimitives.WriteUInt32LittleEndian(bytes.AsSpan(index * sizeof(uint)), words[index]);
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Assert.True(Gen5ShaderTranslator.TryDecodeProgram(new SharpEmu.HLE.CpuContext(new WordMemory(bytes), SharpEmu.HLE.Generation.Gen5),
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0x1000, out var program, out var decodeError), decodeError);
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var (plan, resources, layout) = Prepare(program, userDataCount: 12);
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var request = new ShaderCompileRequest(plan, resources, layout)
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{
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LocalSizeX = 64, WaveSize = 64, EnableExecGuardElision = false,
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ComputeSystemRegisters = new Gen5ComputeSystemRegisters(12, null, null, null),
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};
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Assert.True(Gen5SpirvTranslator.TryCompileProgram(request, out var shader, out var error), error);
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Assert.NotNull(fixture.Vulkan);
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using var harness = new ImageTestHarness(fixture.Vulkan);
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using var runner = new LayoutComputeRunner(harness, request, shader.Spirv);
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harness.AssertNoValidationMessages();
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}
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private sealed class WordMemory(byte[] bytes) : SharpEmu.HLE.ICpuMemory
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{
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public bool TryRead(ulong address, Span<byte> destination)
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{
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if (address < 0x1000 || address - 0x1000 > (ulong)(bytes.Length - destination.Length)) return false;
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bytes.AsSpan((int)(address - 0x1000), destination.Length).CopyTo(destination);
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return true;
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}
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public bool TryWrite(ulong address, ReadOnlySpan<byte> source) => false;
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}
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[Fact]
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public void ASavedExec_RestoresAfterAHalfMaskedBody()
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{
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if (!Ready()) return;
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Lane();
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Add(MoveVector(0, 4, 1));
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CompareTo("VCmpGeU32", 10, Gen5Operand.Vector(2), Operand(28));
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Add(Sop1(0, "SAndSaveexecB64", 12, Gen5Operand.Scalar(10)));
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Add(MoveVector(0, 4, 2));
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Add(Sop2(0, "SOrB64", Exec, Gen5Operand.Scalar(Exec), Gen5Operand.Scalar(12)));
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Add(Vop2(0, "VAddU32", 4, Operand(10), Gen5Operand.Vector(4)));
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var lanes = Run();
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for (uint lane = 0; lane < 64; lane++)
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{
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Assert.Equal(lane >= 28 ? 12u : 11u, lanes[lane]);
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}
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}
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}
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