Preserve combined mip-tail refresh and export routing while taking upstream stencil and no-pixel-stage handling. Adapt upstream uint flags and wave64 exchange to per-register shader state; retain upstream LDS sizing and phase synchronization. |
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| .. | ||
| BlitShaders.cs | ||
| Gen5SpirvShader.cs | ||
| Gen5SpirvTranslator.Alu.cs | ||
| Gen5SpirvTranslator.DataShareSwizzle.cs | ||
| Gen5SpirvTranslator.Interpolation.cs | ||
| Gen5SpirvTranslator.RayIntersect.cs | ||
| Gen5SpirvTranslator.Resources.cs | ||
| Gen5SpirvTranslator.cs | ||
| SharpEmu.ShaderCompiler.Vulkan.csproj | ||
| SpirvFixedShaders.cs | ||
| SpirvModuleBuilder.cs | ||
| TilerShaders.cs | ||