perf(shader): skip the tiny product check that a constant factor settles
With f32 denormals flushed, every f32 multiply and fma checks whether the exact product is below 2^-126 (#1850): two exponent extracts, a 32-bit significand multiply-high and a chain of compares and selects. When a factor is a literal or inline constant, its exponent settles the check during translation: - a factor that is zero (after the input flush), infinite, NaN or at least 1 in magnitude never gives a tiny product, so the check is not emitted; - a power-of-two factor never carries out of the significand product, so the multiply-high is not emitted. Constant sources are folded with their abs, neg and denormal flush, so the factor reaches the check as a constant.
This commit is contained in:
Karan Vora
parent
6cc0503dac
commit
809178603f
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@ -931,6 +931,14 @@ if(BUILD_TESTING)
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set_tests_properties(vector_fused_multiply_add PROPERTIES ENVIRONMENT_MODIFICATION
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"PATH=path_list_prepend:$<TARGET_FILE_DIR:libc>")
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endif()
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add_test_executable(vector_constant_factor_tininess_tests ${LIBS_INCLUDE_DIR}/tests/VectorConstantFactorTininess.cpp)
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target_link_libraries(vector_constant_factor_tininess_tests PRIVATE shader_recompiler_agc_driver libc)
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configure_windows_unwind(vector_constant_factor_tininess_tests)
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add_test(NAME vector_constant_factor_tininess COMMAND vector_constant_factor_tininess_tests)
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if(WIN32)
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set_tests_properties(vector_constant_factor_tininess PROPERTIES ENVIRONMENT_MODIFICATION
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"PATH=path_list_prepend:$<TARGET_FILE_DIR:libc>")
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endif()
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add_test_executable(scalar_saveexec_tests ${LIBS_INCLUDE_DIR}/tests/ScalarSaveexec.cpp)
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target_link_libraries(scalar_saveexec_tests PRIVATE shader_recompiler_agc_driver libc)
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configure_windows_unwind(scalar_saveexec_tests)
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@ -0,0 +1,165 @@
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#include "prx/libSceAgcDriver/Execution/include/VulkanDevice.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/Draw.hpp"
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#include "Recompiler.hpp"
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#include "VulkanTestDevice.hpp"
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#include <algorithm>
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#include <array>
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#include <cstdint>
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#include <cstdio>
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#include <iostream>
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#include <optional>
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#include <stdexcept>
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#include <string>
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#include <vector>
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namespace {
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using AgcDriver::Graphics::Require;
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using ShaderRecompiler::ShaderStage;
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constexpr std::uint32_t Threads = 32;
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constexpr std::uint32_t Inputs = 4;
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constexpr std::uint32_t Results = 16;
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alignas(256) std::array<std::uint32_t, Threads * Inputs> Input{};
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alignas(256) std::array<std::uint32_t, Threads * Results> Output{};
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alignas(256) constexpr std::array<std::uint32_t, 48> Code{
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0x34020084u, 0x34060086u, 0xe0381000u, 0x80000401u, 0xbf8c3f70u,
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0x7e3402f4u, 0x7e3602f0u, 0x7e3802ffu, 0x3f7ffffeu, 0x7e3a02f2u, 0x7e3c02ffu, 0x00400000u, 0x7e3e02f6u,
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0x7e4002ffu, 0x3e800000u, 0x7e4202f4u,
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0x101408f4u, 0x1016091au,
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0x101808f0u, 0x101a091bu,
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0x101c08ffu, 0x3f7ffffeu, 0x101e091cu,
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0x102008ffu, 0x3f800000u, 0x1022091du,
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0x102408ffu, 0x00400000u, 0x1026091eu,
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0x0e2808f6u, 0x0e2a091fu,
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0x582c0b04u, 0x3e800000u, 0xd54b0017u, 0x04164104u,
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0xd54b0218u, 0x4415e904u, 0xd54b0219u, 0x44164304u,
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0xe0781000u, 0x80010a03u, 0xe0781010u, 0x80010e03u, 0xe0781020u, 0x80011203u, 0xe0781030u, 0x80011603u,
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0xbf810000u,
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};
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constexpr std::uint32_t Rows[32][2] = {
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{0x00800000u, 0x00000000u}, {0x80800000u, 0x00000000u}, {0x00800001u, 0x00000000u}, {0x00ffffffu, 0x00000000u},
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{0x01000000u, 0x00000000u}, {0x017fffffu, 0x00000000u}, {0x01800000u, 0x00000000u}, {0x00000001u, 0x00000000u},
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{0x807fffffu, 0x00000000u}, {0x00000000u, 0x00000000u}, {0x80000000u, 0x80000000u}, {0x7f800000u, 0x00000000u},
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{0xff800000u, 0x00000000u}, {0x7fc00000u, 0x00000000u}, {0x7f7fffffu, 0x00000000u}, {0x3f800000u, 0x00000000u},
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{0xbf800000u, 0x3f800000u}, {0x00c00000u, 0x00000000u}, {0x80ffffffu, 0x80000000u}, {0x01000001u, 0x00000000u},
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{0x3f7fffffu, 0x00000000u}, {0x40490fdbu, 0x00000000u}, {0x00fffffeu, 0x00000000u}, {0x81800000u, 0x00000000u},
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{0x017ffffeu, 0x00000000u}, {0x01800001u, 0x00000000u}, {0x0080ffffu, 0x00000000u}, {0x7f000000u, 0x00000000u},
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{0x00800000u, 0x3f800000u}, {0x817fffffu, 0x80000000u}, {0x017fffffu, 0x00800000u}, {0x017fffffu, 0x80000001u}
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};
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constexpr const char* Names[8] = {
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"v_mul_f32 2.0",
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"v_mul_f32 0.5",
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"v_mul_f32 0x3f7ffffe",
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"v_mul_f32 0x3f800000",
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"v_mul_f32 0x00400000",
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"v_mul_legacy_f32 4.0",
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"v_fmamk_f32 0x3e800000",
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"v_fma_f32 -|2.0|"
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};
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struct Pinned {
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std::uint32_t tid;
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std::uint32_t pair;
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std::uint32_t value;
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};
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constexpr std::array<Pinned, 6> TinyProducts{{
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{0u, 2u, 0x00000000u},
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{3u, 1u, 0x00000000u},
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{18u, 1u, 0x80000000u},
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{5u, 6u, 0x00000000u},
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{29u, 6u, 0x80000000u},
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{31u, 6u, 0x00000000u},
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}};
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std::array<std::uint32_t, 4> BufferDescriptor(const void* data, std::uint32_t bytes) {
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const auto address = reinterpret_cast<std::uintptr_t>(data);
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return {static_cast<std::uint32_t>(address), static_cast<std::uint32_t>((address >> 32u) & 0xffffu), bytes, 0x31016facu};
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}
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std::string Hex(std::uint32_t value) {
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char text[16];
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std::snprintf(text, sizeof(text), "0x%08x", value);
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return text;
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}
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bool IsNan(std::uint32_t value) {
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return (value & 0x7fffffffu) > 0x7f800000u;
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}
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void Run(AgcDriver::VulkanDevice& device, const std::optional<ShaderRecompiler::ShaderFloatMode>& floatMode) {
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Input.fill(0u);
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for (std::uint32_t tid = 0; tid < Threads; ++tid) std::copy(std::begin(Rows[tid]), std::end(Rows[tid]), &Input[tid * Inputs]);
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Output.fill(0xdeadbeefu);
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std::vector<std::uint32_t> userData(8, 0u);
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const auto input = BufferDescriptor(Input.data(), static_cast<std::uint32_t>(Input.size() * 4u));
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const auto output = BufferDescriptor(Output.data(), static_cast<std::uint32_t>(Output.size() * 4u));
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std::copy(input.begin(), input.end(), userData.begin());
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std::copy(output.begin(), output.end(), userData.begin() + 4);
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const std::span<const std::uint32_t> code(Code);
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const std::array<ShaderRecompiler::MemoryRegion, 1> memory{{{reinterpret_cast<std::uintptr_t>(code.data()), std::as_bytes(code)}}};
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const ShaderRecompiler::ShaderComputeStageInfo compute{{Threads, 1, 1}, 0u, {false, false, false}, false, 1};
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ShaderRecompiler::RecompileRequest request{
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{ShaderStage::Compute, reinterpret_cast<std::uintptr_t>(code.data()), code, 0, {}},
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{32, 0, userData, compute, std::nullopt, std::nullopt, memory},
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device.Target(),
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{0, 0, 0, 128}
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};
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request.useCache = false;
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request.context.floatMode = floatMode;
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const auto result = ShaderRecompiler::Recompile(request);
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device.Dispatch(result, 1, 1, 1, {}, reinterpret_cast<std::uintptr_t>(code.data()));
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device.WaitIdle();
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}
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void Check(const char* mode) {
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for (std::uint32_t tid = 0; tid < Threads; ++tid) {
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const std::uint32_t* out = &Output[tid * Results];
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for (std::uint32_t pair = 0; pair < 8u; ++pair) {
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const std::uint32_t constant = out[pair * 2u];
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const std::uint32_t reg = out[pair * 2u + 1u];
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const std::string where = std::string("f32 constant factor: lane ") + std::to_string(tid) + " " + mode + " " + Names[pair];
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if (IsNan(reg)) {
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Require(IsNan(constant), where + " is " + Hex(constant) + " with a constant and a NaN with a register");
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continue;
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}
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Require(constant == reg, where + " is " + Hex(constant) + " with a constant and " + Hex(reg) + " with a register");
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}
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}
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}
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void CheckTinyProducts(const char* mode) {
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for (const Pinned& pinned : TinyProducts) {
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const std::uint32_t actual = Output[pinned.tid * Results + pinned.pair * 2u];
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Require(actual == pinned.value, std::string("f32 constant factor: lane ") + std::to_string(pinned.tid) + " " + mode + " " + Names[pinned.pair] + " is " + Hex(actual) + ", expected the flushed tiny product " + Hex(pinned.value));
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}
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}
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}
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int main() {
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try {
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const auto device = OpenVulkanTestDevice();
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if (!device) return VulkanTestSkipped;
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Run(*device, std::nullopt);
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Check("no float mode");
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CheckTinyProducts("no float mode");
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Run(*device, ShaderRecompiler::ShaderFloatMode{0xc0u, true, false, false});
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Check("IEEE=0 f32 denormals flushed");
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CheckTinyProducts("IEEE=0 f32 denormals flushed");
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Run(*device, ShaderRecompiler::ShaderFloatMode{0x00u, false, true, false});
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Check("IEEE=1 all denormals flushed");
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CheckTinyProducts("IEEE=1 all denormals flushed");
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Run(*device, ShaderRecompiler::ShaderFloatMode{0xf0u, true, false, false});
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Check("f32 denormals kept");
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std::puts("f32 constant factor tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@ -0,0 +1,94 @@
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#include "Translation/TranslationContext.hpp"
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#include "RdnaDecoder/RdnaVectorOpDecoder.hpp"
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#include <cstdint>
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#include <iostream>
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#include <span>
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#include <stdexcept>
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#include <string>
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#include <vector>
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using namespace ShaderRecompiler;
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namespace {
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enum class Tininess {
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None,
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ExponentsOnly,
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Full,
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};
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void Require(bool value, const std::string& message) {
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if (!value) throw std::runtime_error("f32 constant factor: " + message);
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}
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const IrBlock& Translate(IrProgram& program, const std::string& name, const std::vector<std::uint32_t>& words, RdnaOpcode opcode, std::uint32_t floatMode) {
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const RdnaInstruction instruction = DecodeRdnaVectorOp(std::span<const std::uint32_t>(words), 0u);
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Require(instruction.op == opcode, name + " decodes to another opcode");
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Require(instruction.wordCount == words.size(), name + " has the wrong length");
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auto& block = program.CreateBlock();
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program.SetEntryBlock(block);
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TranslationContext context(program, block, 256);
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context.SetFloatMode(ShaderFloatMode{floatMode, true, false, false});
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context.TranslateInstruction(instruction);
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return block;
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}
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void Check(const std::string& name, const std::vector<std::uint32_t>& words, RdnaOpcode opcode, Tininess expected, std::uint32_t floatMode = 0xc0u) {
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IrProgram program;
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const auto& block = Translate(program, name, words, opcode, floatMode);
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std::uint32_t multiplyHigh = 0u;
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std::uint32_t tinyCompares = 0u;
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for (const auto* value : block.Instructions()) {
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if (value->Opcode() == IrOpcode::UMulHi) ++multiplyHigh;
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if (value->Opcode() == IrOpcode::ULessThan32 && value->Argument(1)->HasImmediate() && value->Argument(1)->ImmediateU32() == 128u) ++tinyCompares;
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}
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const std::uint32_t expectedCompares = expected == Tininess::None ? 0u : 1u;
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const std::uint32_t expectedMultiplyHigh = expected == Tininess::Full ? 1u : 0u;
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Require(tinyCompares == expectedCompares, name + " emits " + std::to_string(tinyCompares) + " tiny product checks, expected " + std::to_string(expectedCompares));
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Require(multiplyHigh == expectedMultiplyHigh, name + " emits " + std::to_string(multiplyHigh) + " significand products, expected " + std::to_string(expectedMultiplyHigh));
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}
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void CheckFoldedSource(const std::string& name, const std::vector<std::uint32_t>& words, RdnaOpcode opcode, IrOpcode product, std::uint32_t index, std::uint32_t expected) {
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IrProgram program;
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const auto& block = Translate(program, name, words, opcode, 0xc0u);
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for (const auto* value : block.Instructions()) {
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if (value->Opcode() != product) continue;
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const IrValue* source = value->Argument(index);
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Require(source->Opcode() == IrOpcode::BitCastF32U32 && source->Argument(0)->HasImmediate(), name + " source " + std::to_string(index) + " is not a constant");
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Require(source->Argument(0)->ImmediateU32() == expected, name + " source " + std::to_string(index) + " is folded to the wrong constant");
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return;
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}
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Require(false, name + " emits no product");
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}
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}
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int main() {
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try {
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Check("v_mul_f32 v5, v6, v7", {0x100a0f06u}, RdnaOpcode::VMulF32, Tininess::Full);
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Check("v_mul_f32 v5, 2.0, v7", {0x100a0ef4u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, -4.0, v7", {0x100a0ef7u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, 1.0, v7", {0x100a0ef2u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, 0x7f800000, v7", {0x100a0effu, 0x7f800000u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, 0x00400000, v7", {0x100a0effu, 0x00400000u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, 1, v7", {0x100a0e81u}, RdnaOpcode::VMulF32, Tininess::None);
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Check("v_mul_f32 v5, 0.5, v7", {0x100a0ef0u}, RdnaOpcode::VMulF32, Tininess::ExponentsOnly);
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Check("v_mul_f32 v5, 0x3e800000, v7", {0x100a0effu, 0x3e800000u}, RdnaOpcode::VMulF32, Tininess::ExponentsOnly);
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Check("v_mul_f32 v5, 0x3f7fffff, v7", {0x100a0effu, 0x3f7fffffu}, RdnaOpcode::VMulF32, Tininess::Full);
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Check("v_mul_f32 v5, 0.15915494, v7", {0x100a0ef8u}, RdnaOpcode::VMulF32, Tininess::Full);
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Check("v_mul_legacy_f32 v5, 4.0, v7", {0x0e0a0ef6u}, RdnaOpcode::VMulLegacyF32, Tininess::None);
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Check("v_fmamk_f32 v5, v6, 0x40400000, v7", {0x580a0f06u, 0x40400000u}, RdnaOpcode::VMadmkF32, Tininess::None);
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Check("v_fmaak_f32 v5, v6, v7, 0x40400000", {0x5a0a0f06u, 0x40400000u}, RdnaOpcode::VMadakF32, Tininess::Full);
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Check("v_fma_f32 v5, v6, -|2.0|, v7", {0xd54b0205u, 0x441de906u}, RdnaOpcode::VFmaF32, Tininess::None);
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Check("v_fma_f32 v5, v6, -|0.5|, v7", {0xd54b0205u, 0x441de106u}, RdnaOpcode::VFmaF32, Tininess::ExponentsOnly);
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Check("v_mul_f32 v5, 2.0, v7 with f32 denormals kept", {0x100a0ef4u}, RdnaOpcode::VMulF32, Tininess::None, 0xf0u);
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Check("v_mul_f32 v5, v6, v7 with f32 denormals kept", {0x100a0f06u}, RdnaOpcode::VMulF32, Tininess::None, 0xf0u);
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CheckFoldedSource("v_fma_f32 v5, v6, -|2.0|, v7", {0xd54b0205u, 0x441de906u}, RdnaOpcode::VFmaF32, IrOpcode::FPFma32, 1u, 0xc0000000u);
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CheckFoldedSource("v_mul_f32 v5, 0x00400000, v7", {0x100a0effu, 0x00400000u}, RdnaOpcode::VMulF32, IrOpcode::FPMul32, 0u, 0x00000000u);
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CheckFoldedSource("v_mul_f32 v5, 0x80400000, v7", {0x100a0effu, 0x80400000u}, RdnaOpcode::VMulF32, IrOpcode::FPMul32, 0u, 0x80000000u);
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@ -12,6 +12,24 @@ DppMoveFlags dppFlags(const RdnaOperand& operand) {
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return {control, static_cast<std::uint8_t>(operand.dppRowMask), static_cast<std::uint8_t>(operand.dppBankMask), operand.dppFetchInactive, operand.dppBoundCtrl};
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}
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const IrValue* constantF32Bits(const IrValue& value) {
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if (value.Opcode() != IrOpcode::BitCastF32U32) return nullptr;
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const IrValue* bits = value.Argument(0);
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return bits->HasImmediate() ? bits : nullptr;
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}
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bool keepsProductOutOfTinyRange(const IrValue& factor) {
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const IrValue* bits = constantF32Bits(factor);
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if (bits == nullptr) return false;
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const std::uint32_t exponent = (bits->ImmediateU32() >> 23u) & 0xffu;
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return exponent == 0u || exponent >= 127u;
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}
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bool hasUnitSignificand(const IrValue& factor) {
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const IrValue* bits = constantF32Bits(factor);
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return bits != nullptr && (bits->ImmediateU32() & 0x007fffffu) == 0u;
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}
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}
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const RdnaOperand& TranslationContext::sourceAt(const RdnaInstruction& inst, std::uint32_t index) {
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@ -127,12 +145,16 @@ RdnaOperand TranslationContext::plainOperand(const RdnaOperand& operand) {
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IrU32 TranslationContext::flushF32Denormal(IrU32 bits) {
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if ((f32DenormalFlush & 1u) == 0u) return bits;
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if (bits.Value().HasImmediate()) {
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const std::uint32_t value = bits.Value().ImmediateU32();
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||||
return (value & 0x7f800000u) == 0u ? IrU32(ir.Constant(value & 0x80000000u)) : bits;
|
||||
}
|
||||
const IrU1 denormal(ir.IEqual(ir.BitwiseAnd(bits.Value(), ir.Constant(0x7f800000u)), ir.Constant(0u)));
|
||||
return IrU32(ir.Select(denormal.Value(), ir.BitwiseAnd(bits.Value(), ir.Constant(0x80000000u)), bits.Value()));
|
||||
}
|
||||
|
||||
IrF32 TranslationContext::flushTinyProduct(IrValue* lhs, IrValue* rhs, IrValue* product, IrValue* addend) {
|
||||
if ((f32DenormalFlush & 2u) == 0u) return IrF32(*product);
|
||||
if ((f32DenormalFlush & 2u) == 0u || keepsProductOutOfTinyRange(*lhs) || keepsProductOutOfTinyRange(*rhs)) return IrF32(*product);
|
||||
IrValue& lhsBits = ir.BitCastU32(*lhs);
|
||||
IrValue& rhsBits = ir.BitCastU32(*rhs);
|
||||
const auto exponent = [&](IrValue& bits) -> IrValue& { return ir.Emit(IrOpcode::BitFieldUExtract, IrType::U32, {&bits, &ir.Constant(23u), &ir.Constant(8u)}); };
|
||||
|
|
@ -140,7 +162,7 @@ IrF32 TranslationContext::flushTinyProduct(IrValue* lhs, IrValue* rhs, IrValue*
|
|||
IrValue& lhsExponent = exponent(lhsBits);
|
||||
IrValue& rhsExponent = exponent(rhsBits);
|
||||
const auto finiteNonZero = [&](IrValue& value) -> IrValue& { return ir.LogicalAnd(ir.INotEqual(value, ir.Constant(0u)), ir.INotEqual(value, ir.Constant(0xffu))); };
|
||||
IrValue& carry = ir.Select(ir.UGreaterThan(ir.Emit(IrOpcode::UMulHi, IrType::U32, {&significand(lhsBits), &significand(rhsBits)}), ir.Constant(0x7fffu)), ir.Constant(1u), ir.Constant(0u));
|
||||
IrValue& carry = hasUnitSignificand(*lhs) || hasUnitSignificand(*rhs) ? ir.Constant(0u) : ir.Select(ir.UGreaterThan(ir.Emit(IrOpcode::UMulHi, IrType::U32, {&significand(lhsBits), &significand(rhsBits)}), ir.Constant(0x7fffu)), ir.Constant(1u), ir.Constant(0u));
|
||||
IrValue* tiny = &ir.LogicalAnd(ir.LogicalAnd(finiteNonZero(lhsExponent), finiteNonZero(rhsExponent)), ir.ULessThan(ir.IAdd(ir.IAdd(lhsExponent, rhsExponent), carry), ir.Constant(128u)));
|
||||
if (addend != nullptr) tiny = &ir.LogicalAnd(*tiny, ir.IEqual(ir.BitwiseAnd(ir.BitCastU32(*addend), ir.Constant(0x7fffffffu)), ir.Constant(0u)));
|
||||
IrValue& sign = ir.BitwiseAnd(ir.BitwiseXor(lhsBits, rhsBits), ir.Constant(0x80000000u));
|
||||
|
|
@ -173,11 +195,17 @@ IrValue* TranslationContext::readOperand(const RdnaOperand& operand, IrType type
|
|||
return &ir.ConstructU64(pair[0].Value(), pair[1].Value());
|
||||
}
|
||||
IrU32 bits = applyBitSourceModifiers(operand, readRawU32(operand));
|
||||
if (operand.absolute) {
|
||||
bits = IrU32(ir.BitwiseAnd(bits.Value(), ir.Constant(0x7fffffffu)));
|
||||
}
|
||||
if (operand.negate) {
|
||||
bits = IrU32(ir.BitwiseXor(bits.Value(), ir.Constant(0x80000000u)));
|
||||
if (bits.Value().HasImmediate()) {
|
||||
const std::uint32_t value = bits.Value().ImmediateU32();
|
||||
const std::uint32_t magnitude = operand.absolute ? value & 0x7fffffffu : value;
|
||||
bits = IrU32(ir.Constant(operand.negate ? magnitude ^ 0x80000000u : magnitude));
|
||||
} else {
|
||||
if (operand.absolute) {
|
||||
bits = IrU32(ir.BitwiseAnd(bits.Value(), ir.Constant(0x7fffffffu)));
|
||||
}
|
||||
if (operand.negate) {
|
||||
bits = IrU32(ir.BitwiseXor(bits.Value(), ir.Constant(0x80000000u)));
|
||||
}
|
||||
}
|
||||
if (TypesOverlap(type, IrType::F32) && !TypesOverlap(type, IrType::U32)) {
|
||||
return &ir.BitCastF32(flushF32Denormal(bits).Value());
|
||||
|
|
|
|||
Loading…
Reference in New Issue