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AnyPS5/core/relinker/codegen/include/codegen
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Adrià Franch 5fc16a9548 feat(relinker): lower SHA-256 instructions with a memory operand 
SHA256RNDS2/MSG1/MSG2 with a memory source made `--to-intel` fail the
whole relink. The stub now spills a scratch xmm, loads the operand into
it with MOVDQU (AMD does not fault on a misaligned SHA operand, so the
unaligned load keeps that behaviour) and runs the register-form
lowering. RSP-based operands get the spill depth added to their
displacement. RIP-relative operands still fail: the stub runs at a
different address.

Co-Authored-By: Claude <noreply@anthropic.com>
 		2026-10-04 08:21:40 +02:00
..
x86 feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
CodegenException.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
CodegenTypes.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
IAmd64OnlyConverter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionDecoder.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionRewriter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
IInstructionScanner.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00