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AnyPS5/core/relinker/codegen/include/codegen/x86
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Adrià Franch 5fc16a9548 feat(relinker): lower SHA-256 instructions with a memory operand 
SHA256RNDS2/MSG1/MSG2 with a memory source made `--to-intel` fail the
whole relink. The stub now spills a scratch xmm, loads the operand into
it with MOVDQU (AMD does not fault on a misaligned SHA operand, so the
unaligned load keeps that behaviour) and runs the register-form
lowering. RSP-based operands get the spill depth added to their
displacement. RIP-relative operands still fail: the stub runs at a
different address.

Co-Authored-By: Claude <noreply@anthropic.com>
 		2026-10-04 08:21:40 +02:00
..
Amd64OnlySubstitutionTable.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
Amd64OnlySubstitutionTypes.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
ClzeroLowering.hpp feat(relinker): lower CLZERO for --to-intel 2026-10-01 12:30:35 +02:00
ClzeroOperands.hpp feat(relinker): lower CLZERO for --to-intel 2026-10-01 12:30:35 +02:00
DecodedInstruction.hpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
IAmd64OnlyInstructionMatcher.hpp feat(relinker): lower register-form EXTRQ and relocate following instructions for short sites 2026-09-28 16:37:15 +13:00
ReciprocalLowering.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
ReciprocalOperands.hpp fix(relinker): lower VRSQRTPS and VRCPPS to correctly rounded results for --to-intel 2026-10-04 14:40:16 +13:00
Sha1Lowering.hpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
Sha1Operands.hpp feat(relinker): lower SHA-1 instructions for --to-intel 2026-10-03 07:40:41 +02:00
Sha256Lowering.hpp feat(relinker): lower SHA-256 instructions for --to-intel 2026-10-01 00:20:43 +02:00
Sha256Operands.hpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
Sse4aLowering.hpp feat(relinker): lower SHA-256 instructions for --to-intel 2026-10-01 00:20:43 +02:00
Sse4aOperands.hpp feat(relinker): --to-intel lowers SSE4a sites to same-length jumps into an appended stub section 2026-09-26 19:00:39 -07:00
StubBodyBuilder.hpp feat(relinker): lower SHA-256 instructions with a memory operand 2026-10-04 08:21:40 +02:00
X64Assembler.hpp refactor(codegen): separated x86 assembler 2026-09-13 17:04:02 +03:00
X64InstructionDecoder.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
X64InstructionRewriter.hpp refactor(core): seprated folders for relinker and libs 2026-09-11 14:53:01 +03:00
X64OpcodeConstants.hpp fix(relinker): decode EMMS without a ModRM byte 2026-09-29 07:39:01 +10:00
X64Register.hpp refactor(codegen): separated x86 assembler 2026-09-13 17:04:02 +03:00