AnyPS5/core/shader/recompiler/IntermediateRepresentation/include/IntermediateRepresentation
thibaut 2ecbbe40a3 fix(shader): keep direct VGPR accesses in SSA when the window has only relative reads
A program that uses relative VGPR addressing placed every register from the
lowest relatively addressed one upward in the window array, so even direct
accesses became array loads and stores. A descriptor spilled with v_writelane
and restored with v_readlane then lost its definition, and resource analysis
refused GetSamplerResource with ReadLane(LoadVectorWindow(Immediate)) (GTA V,
PPSA04264, shader 0x25a889400).

When the program has no indexed writes (v_movreld, v_movrelsd, v_swaprel),
direct accesses stay SSA registers and each direct write is mirrored into the
window for the relative reads.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01V1W4jdNSKTV7xwuS6xQPJV
2026-10-13 13:59:35 +13:00
..
IrMetadata fix(shader): keep direct VGPR accesses in SSA when the window has only relative reads 2026-10-13 13:59:35 +13:00
GuestRegister.hpp feat(shader): rdna memory op decoder impl 2026-09-15 07:07:50 +03:00
IrBlock.hpp feat(shader): rdna memory op decoder impl 2026-09-15 07:07:50 +03:00
IrBuilder.hpp perf(recompiler): keep relatively addressed vector registers in a window array 2026-10-11 17:26:18 +00:00
IrBuilderInternal.hpp feat(shader): ir builder convertions impl 2026-09-15 12:00:21 +03:00
IrMetadata.hpp refactor(shader): refactor ir metadata types to separated headers 2026-09-18 12:28:41 +03:00
IrOpcode.hpp Merge pull request #3856 from ErenYeager1836/carry/recompiler-vector-window 2026-10-12 00:10:58 +02:00
IrProgram.hpp feat(shader): rdna memory op decoder impl 2026-09-15 07:07:50 +03:00
IrType.hpp feat(shader): rdna memory op decoder impl 2026-09-15 07:07:50 +03:00
IrValue.hpp perf(recompiler): memoize SRT evaluation in a flat table and inline IrValue's hot accessors 2026-10-03 10:05:11 +13:00