87166eed94
refactor(shader): reduce dispatcher state overhead
2026-08-21 03:32:47 +02:00
6e9f162bd4
refactor(shader): compact paired 64-bit lowering
2026-08-21 03:32:47 +02:00
8063822243
refactor(shader): preserve native scalar memory operations
2026-08-21 03:32:47 +02:00
c236ba713d
refactor(shader): preserve native wide shared operations
2026-08-21 03:32:47 +02:00
c9e942a972
refactor(shader): compact whole-quad mask lowering
2026-08-21 03:32:47 +02:00
5383972e96
refactor(shader): preserve native wide buffer operations
2026-08-21 03:32:47 +02:00
3ea2099245
refactor(shader): simplify buffer access emission
2026-08-21 03:32:47 +02:00
49145c1902
refactor(shader): emit structured phis natively
2026-08-21 03:32:47 +02:00
d34e30d892
refactor(shader): emit SPIR-V declarations on demand
2026-08-21 03:32:47 +02:00
e1bcc298a0
refactor(shader): remove register-state compatibility paths
2026-08-21 03:32:47 +02:00
33545ca6c4
test(shader): establish SPIR-V size baselines
2026-08-21 03:32:47 +02:00
7e42513faf
perf(shader): cache analysis ( #259 )
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perf(shader): cache SPIR-V requirement analysis
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-08-19 00:50:13 +02:00
596ecdcca0
Fix shader CFG structurization for nested early exits
2026-08-19 00:14:51 +02:00
377fb8f50a
shader: use ISA-style decoder opcode names
2026-08-18 03:53:45 +02:00
01275fb211
shader_recompiler: rename/clean up typed SSA SPIR-V emitter
2026-08-18 03:53:45 +02:00
5970c4ef95
shader_recompiler: remove legacy SPIR-V emitter
2026-08-18 03:53:44 +02:00
8ce06ccdf6
shader: route nested shared regions
2026-08-18 03:53:44 +02:00
1dbac4fd79
shader: repair nested merge structurization
2026-08-18 03:53:44 +02:00
d80fbea51d
shader: resolve subtractive dword SETPC tables
2026-08-18 03:53:44 +02:00
0f3540b1ff
shader: unify stage input metadata
2026-08-18 03:53:44 +02:00
7850cbeaef
rename legacy Graphics -> Agc
2026-08-18 03:53:43 +02:00
4e343408dc
graphics: size compute LDS from shader state
2026-08-18 03:53:43 +02:00
1c4171c9eb
graphics: accept SDWA byte conversion sources
2026-08-18 03:53:43 +02:00
443bbcbf90
graphics: separate scalar address bindings
2026-08-18 03:53:43 +02:00
484433b180
shader: fix V_ADD_NC_U32
2026-08-18 03:53:42 +02:00
7556a74f19
shader: implement s_bfe_i32
2026-08-18 03:53:42 +02:00
b4809e7170
Fix SPIR-V float control contract (Preserve FP32 Inf and NaN)
2026-08-18 03:53:42 +02:00
0df20eb300
fix opcode regression
2026-08-18 03:53:42 +02:00
5bfdf4267e
Optimize decoder
2026-08-18 03:53:42 +02:00
f453a752bb
shader: snapshot wide SMEM sources before writes
2026-08-18 03:53:42 +02:00
28a913894d
graphics: implement RDNA2 64-bit first-set-bit
2026-08-18 03:53:42 +02:00
13e87a8e58
graphics: implement RDNA2 alignbyte shader opcode
2026-08-18 03:53:42 +02:00
9c316e6988
shader: implement RDNA2 v_cmp_gt_u64
2026-08-18 03:53:42 +02:00
b42380ced6
shader_recompiler: add SSA
2026-08-18 03:53:41 +02:00
4980efa9b7
refactor(subsystems&ime): RAII lifecycle
2026-08-11 16:12:38 +02:00
21aa7b66ce
graphics: replace raw GPU enum values with typed formats
2026-08-11 16:12:38 +02:00
11b95bed20
graphics: simplify render target format and color mapping resolution
2026-08-11 16:12:38 +02:00
ac64d202af
shader: implement BUFFER_ATOMIC_FMAX
2026-08-05 02:59:28 +02:00
df44ad3fac
shader: implement BUFFER_ATOMIC_FMIN, unhandled IR opcode now fails
2026-08-05 02:59:28 +02:00
0a2f4814ac
refactor(shader): centralize opcode metadata and lookup paths
2026-08-05 02:59:28 +02:00
9a3468e3a0
shader: implement V_MIN_U32
2026-08-05 02:59:28 +02:00
73da43a7be
shader: implement V_CNDMASK_B32
2026-08-05 02:59:28 +02:00
aa88d94755
shader: implement V_SUB_NC_U32
2026-08-05 02:59:27 +02:00
51562cd8d2
tests: use valid image descriptors in shader CFG cases
2026-08-05 02:59:27 +02:00
44d7f2a3e8
shader cfg: handle shared early exits
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Duplicate small shared exit tails so each selection gets its own merge block. This keeps overlapping early-exit ladders on structured SPIR-V and adds a regression test.
2026-08-02 03:16:08 +02:00
2dcb90066c
shader cfg: normalize loop structure
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Give loops one header and one continue path before SPIR-V generation. This handles conditional headers and multiple latches without falling back to a dispatcher.
2026-08-02 03:15:26 +02:00
51a33cc363
shader cfg: handle loop control branches
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Keep simple break, continue, and repeat branches in structured control flow. Split conflicting merge blocks and add regression tests for nested loop exits.
2026-08-02 03:14:39 +02:00
d8a4c83cc7
format src and tests with clang-format
2026-07-31 11:36:12 +02:00
68be13345a
fix(shader): support multisampled depth image loads
2026-07-31 11:36:12 +02:00
212282d693
fix(shader): preserve packed UINT16 MRT exports
2026-07-31 11:36:12 +02:00
nmzik
Senaxx