[SpirvTranslator] Synchronize shared memory phases in multi block shaders
Co-authored-by: TarkusR <90155059+TarkusR@users.noreply.github.com>
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@ -1361,8 +1361,7 @@ public static partial class Gen5SpirvTranslator
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error = string.Empty;
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var block = blocks[blockIndex];
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// One guest wave can span two host subgroups. Keep its shared-memory phases ordered.
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// Restrict added barriers to a single block, where all invocations follow the same path.
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var synchronizeSharedMemory = _emulateWave64 && blocks.Count == 1;
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var synchronizeSharedMemory = _emulateWave64;
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var sharedMemoryPhase = SharedMemoryPhase.None;
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for (var index = block.StartIndex; index < block.EndIndex; index++)
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{
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@ -11,12 +11,14 @@ namespace SharpEmu.ShaderCompiler.Tests;
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public sealed class Gen5SharedMemoryBarrierTests
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{
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[Theory]
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[InlineData(64u, 64u, false, 2)]
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[InlineData(64u, 64u, true, 2)]
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[InlineData(32u, 64u, false, 0)]
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[InlineData(64u, 128u, false, 0)]
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[InlineData(64u, 64u, false, false, 2)]
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[InlineData(64u, 64u, true, false, 2)]
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[InlineData(32u, 64u, false, false, 0)]
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[InlineData(64u, 128u, false, false, 0)]
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[InlineData(64u, 64u, false, true, 2)]
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[InlineData(32u, 64u, false, true, 0)]
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public void SharedMemoryPhases_SynchronizeOnlySingleWaveGroups(
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uint waveSize, uint threadCount, bool explicitBarrier, int expectedBarriers)
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uint waveSize, uint threadCount, bool explicitBarrier, bool splitBlocks, int expectedBarriers)
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{
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var instructions = new List<Gen5ShaderInstruction>
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{
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@ -25,6 +27,8 @@ public sealed class Gen5SharedMemoryBarrierTests
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};
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if (explicitBarrier)
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instructions.Add(new(8, Gen5ShaderEncoding.Sopp, "SBarrier", [0u], [], [], null));
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if (splitBlocks)
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instructions.Add(new(8, Gen5ShaderEncoding.Sopp, "SBranch", [0u], [], [], null));
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instructions.Add(new(12, Gen5ShaderEncoding.Ds, "DsReadB32", [0u, 0u],
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[Gen5Operand.Vector(0)], [Gen5Operand.Vector(2)], new Gen5DataShareControl(0, 0, false)));
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instructions.Add(new(20, Gen5ShaderEncoding.Sopp, "SEndpgm", [0u], [], [], null));
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