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  • win64-main-0565d01 0565d01744

    [AGC] Support VOP3 signed 32-bit multiplies (v_mul_lo_i32, v_mul_hi_i32) (#106)

    Ghost released this 2026-07-13 11:53:19 -04:00 | 508 commits to 1016_part3 since this release

    Two gaps around the VOP3 signed multiplies caused whole-shader SPIR-V
    compilation failures:

    • v_mul_lo_i32 (0x16B) decoded correctly but had no emission case, so
      any shader containing it failed with "unsupported vector opcode
      VMulLoI32". Its low 32 result bits are identical to the unsigned
      multiply in two's complement, so it now shares the v_mul_lo_u32 IMul
      case.
    • v_mul_hi_i32 (0x16C) was missing from the VOP3 decode table entirely
      and decoded as an opaque Vop3Raw16C, which also fails at emission.
      It is now decoded and emitted by sign-extending both operands to
      64 bits, multiplying, and taking the upper 32 bits of the product,
      mirroring the existing v_mul_hi_u32 pattern.

    Opcode numbers verified against LLVM's AMDGPU backend
    (VOP3Instructions.td): V_MUL_LO_U32 gfx10 = 0x169, V_MUL_HI_U32 =
    0x16a, V_MUL_LO_I32 = 0x16b, V_MUL_HI_I32 = 0x16c. Behavior verified
    by decoding and fully compiling a synthetic program containing all
    four multiplies: previously the 0x16C word decoded as Vop3Raw16C and
    compilation failed at the v_mul_lo_i32 instruction; now all four
    decode by name and the program compiles to SPIR-V.

    Co-authored-by: Claude Fable 5 noreply@anthropic.com

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