160521fd78
[GPU] Clear image buffer owners with format-correct fill values
2026-10-13 04:54:37 +03:00
8164636d99
[GPU] Decode repeated FP16 and uint buffer fill words
2026-10-13 04:54:36 +03:00
f19c4ca4d5
[Tests] Cover the written mip statistics report
2026-10-13 03:46:56 +03:00
c61c1602aa
[Presenter] Report bound mip statistics by default and measure on the GPU on request
2026-10-13 03:46:56 +03:00
d0ffcb24d2
[Presenter] Write the bound mip statistics in stream order on the render thread
2026-10-13 03:46:56 +03:00
880270b344
[GPU] Write the interpreter's LOD statistics through the shared report writer
2026-10-13 03:46:56 +03:00
d5332f01ca
[GPU] Write the mip statistics report with its ready marker
2026-10-13 03:46:56 +03:00
fab999316e
[Tests] Cover concurrent resolve answers and release device slabs
2026-10-13 03:46:56 +03:00
6631a665f8
[Presenter] Merge overlapping concurrent resolve ownership answers
2026-10-13 03:46:56 +03:00
002007c323
[GPU] Fill metadata-shaped bounded fills on the host
2026-10-13 03:46:56 +03:00
b26c59460d
[Diagnostics] Report the GPU writers of synchronized DCC metadata
2026-10-13 03:46:56 +03:00
d4276d89f8
[Profile] Count DCC metadata synchronizations and their outcome
2026-10-13 03:46:56 +03:00
e5c2755789
[Profile] Attribute render thread GPU waits to their call sites
2026-10-13 03:46:56 +03:00
22ec74e085
[Profile] Classify what changed in stale resource cache entries
2026-10-13 03:46:56 +03:00
7b730a51fc
[Profile] Count resource cache refusal reasons
2026-10-13 03:46:56 +03:00
8616383a58
[Tests] Cover wave64 subgroups, readbacks, barriers, LOD statistics and packet writes
2026-10-13 03:46:56 +03:00
416464db1e
[AGC] Emit register packets with one write
2026-10-13 03:46:56 +03:00
cd51a9ea2e
[AGC] Emit event and flip packets with one write
2026-10-13 03:46:56 +03:00
8f8737e2d1
[AGC] Emit draw packets with one write
2026-10-13 03:46:56 +03:00
3fba66473b
[AGC] Emit indirect buffer packets with one write
2026-10-13 03:46:56 +03:00
e2ad2084f8
[AGC] Emit dispatch, memory and marker packets with one write
2026-10-13 03:46:56 +03:00
9b552ffb72
[AGC] Emit packets with one write and read the buffer state at once
2026-10-13 03:46:56 +03:00
8c24a40bfa
[HLE] Skip the region lock for writes to CPU-dirty pages
2026-10-13 03:46:56 +03:00
643a565a22
[HLE] Answer GPU span coverage from a snapshot
2026-10-13 03:46:56 +03:00
8f7fa3933f
[HLE] Write single-view guest memory without the region lock
2026-10-13 03:46:56 +03:00
48258b1e50
[Core] Map guest thread priorities one band lower
2026-10-13 03:46:56 +03:00
ca076237c6
[GPU] Memoize texture lookups of DCC images
2026-10-13 03:46:56 +03:00
dc73931dd6
[GPU] Split the post-lookup work out of image lookups
2026-10-13 03:46:56 +03:00
1fbecd3233
[GPU] Skip native binds that repeat the bound state
2026-10-13 03:46:55 +03:00
ae97ac9525
[GPU] Advance a binding epoch when helper passes bind their own state
2026-10-13 03:46:55 +03:00
b179883b5c
[ShaderCompiler] Start pixel append programs without helper lanes
2026-10-13 03:46:55 +03:00
32c9a37b0e
[GPU] Report LOD statistics measured on the GPU
2026-10-13 03:46:55 +03:00
5d6b59eeb8
[GPU] Pack LOD statistics reports from counter words
2026-10-13 03:46:55 +03:00
8d0af3d8f7
[ShaderCompiler] Count the finest mip each pixel sample reaches
2026-10-13 03:46:55 +03:00
a1b44452fa
[GPU] Skip the upload walk when no CPU-dirty page is in range
2026-10-13 03:46:55 +03:00
d2090f47fb
[GPU] Stop reading ahead windows whose copies keep going stale
2026-10-13 03:46:55 +03:00
b5c15a7426
[GPU] Publish read-back pieces that no later write covers
2026-10-13 03:46:55 +03:00
fd2afcd8c8
[GPU] Track GPU write ticks per buffer range
2026-10-13 03:46:55 +03:00
6d69163297
[GPU] Request guest memory barriers through the recording buffer
2026-10-13 03:46:55 +03:00
c622b64ace
[GPU] Merge consecutive memory barrier requests in a recording buffer
2026-10-13 03:46:55 +03:00
0de84e34df
[Diagnostics] Count GPU barriers and rendering scopes
2026-10-13 03:46:55 +03:00
84c830f7ce
[ShaderCompiler] Skip EXEC selects for vector writes no lane observes
2026-10-13 03:46:55 +03:00
d24f6c6a85
[GPU] Compile wave64 compute for 32-lane subgroups when the host lacks wave64
2026-10-13 03:46:55 +03:00
08891b1fef
[ShaderCompiler] Run lane-local wave64 programs as independent half waves
2026-10-13 03:46:55 +03:00
7a6e3d0308
[ShaderCompiler] Run wave64 compute as paired lanes on 32-lane subgroups
2026-10-13 03:46:55 +03:00
4087ab84f8
[ShaderCompiler] Let compile requests ask for 32-lane compute subgroups
2026-10-13 03:46:55 +03:00
5febf063f4
[ShaderCompiler] Declare the SubgroupId built-in
2026-10-13 03:46:55 +03:00
c02f2163f2
[ShaderCompiler] Find vector writes that no later instruction observes
2026-10-13 03:46:55 +03:00
8a0d713665
[ShaderCompiler] Prove wave64 programs whose lanes never read each other
2026-10-13 03:46:55 +03:00
3f01c0e91c
[GPU] Record a frame's draws before its boundary returns to the guest
...
With the command stream on its own thread, a frame boundary only posted its
flush, so the guest resumed while up to 64 items of the frame were still
queued for the render thread. The guest then rewrote per-draw memory
(descriptor tables, rings) that those draws read when recorded, which showed
as black frames and flicker. The boundary now waits for the render thread to
run everything queued before it.
2026-10-13 03:46:55 +03:00
ParantezTech
Astellou